Merge pull request 'main' (#1) from Github_Repos/cvw:main into main

Reviewed-on: #1

.editorconfig

@@ -0,0 +1,5 @@
+root = true
+
+[src/**.sv]
+indent_style = space
+indent_size = 2

.gitignore

@@ -7,14 +7,15 @@ __pycache__/
 .vscode/
 
 #External repos
-addins
 addins/riscv-arch-test/Makefile.include
 addins/riscv-tests/target
+addins/TestFloat-3e/build/Linux-x86_64-GCC/*
+benchmarks/embench/wally*.json
 
 #vsim work files to ignore
 transcript
 vsim.wlf
-pipelined/wlft*
+wlft*
 wlft*
 /imperas-riscv-tests/FunctionRadix_32.addr
 /imperas-riscv-tests/FunctionRadix_64.addr
@@ -28,6 +29,10 @@ testsBP/*/*/*.elf*
 testsBP/*/OBJ/*
 testsBP/*/*.a
 tests/wally-riscv-arch-test/riscv-test-suite/*/I/*/*
+tests/riscof/riscof_work/
+tests/riscof/config32.ini
+tests/riscof/config32e.ini
+tests/riscof/config64.ini
 tests/linux-testgen/linux-testvectors/*
 !tests/linux-testgen/linux-testvectors/tvCopier.py
 !tests/linux-testgen/linux-testvectors/tvLinker.sh
@@ -37,8 +42,8 @@ tests/linux-testgen/buildroot-image-output
 tests/linux-testgen/buildroot-config-src/main.config.old
 tests/linux-testgen/buildroot-config-src/linux.config.old
 tests/linux-testgen/buildroot-config-src/busybox.config.old
-pipelined/regression/slack-notifier/slack-webhook-url.txt
-pipelined/regression/logs
+sim/slack-notifier/slack-webhook-url.txt
+sim/logs
 fpga/generator/IP
 fpga/generator/vivado.*
 fpga/generator/.Xil/*
@@ -52,13 +57,62 @@ examples/asm/sumtest/sumtest
 examples/asm/example/example
 examples/C/sum/sum
 examples/C/fir/fir
+examples/fp/softfloat_demo/softfloat_demo
+examples/fp/fpcalc/fpcalc
+src/fma/fma16_testgen
 linux/devicetree/debug/*
 !linux/devicetree/debug/dump-dts.sh
+linux/testvector-generation/genCheckpoint.gdb
+linux/testvector-generation/silencePipe
+linux/testvector-generation/silencePipe.control
+linux/testvector-generation/fixBinMem
+linux/testvector-generation/qemu-serial
 *.dtb
 synthDC/WORK
 synthDC/alib-52
 synthDC/*.log
 synthDC/*.svf
 synthDC/runs/
+synthDC/newRuns
+synthDC/ppa/PPAruns
+synthDC/ppa/plots
+synthDC/wallyplots/
+synthDC/runArchive
 synthDC/hdl
-/pipelined/regression/power.saif
+sim/power.saif
+tests/fp/vectors/*.tv
+synthDC/Summary.csv
+sim/wkdir
+tests/custom/work
+tests/custom/*/*/*.list
+tests/custom/*/*/*.elf
+tests/custom/*/*/*.map
+tests/custom/*/*/*.memfile
+tests/custom/crt0/*.a
+tests/custom/*/*.elf*
+sim/sd_model.log
+fpga/src/sdc/*
+fpga/src/sdc.tar.gz
+fpga/src/CopiedFiles_do_not_add_to_repo/*
+sim/branch.log
+/fpga/generator/sim/imp-funcsim.v
+/fpga/generator/sim/imp-timesim.sdf
+/fpga/generator/sim/imp-timesim.v
+/fpga/generator/sim/syn-funcsim.v
+external
+sim/results
+tests/wally-riscv-arch-test/riscv-test-suite/rv*i_m/I/src/*.S
+tests/wally-riscv-arch-test/riscv-test-suite/rv*i_m/I/Makefrag
+sim/branch_BP_GSHARE10.log
+sim/branch_BP_GSHARE16.log
+sim/cov/
+sim/covhtmlreport/
+sim/imperas.log
+sim/results-error/
+sim/test1.rep
+sim/vsim.log
+tests/coverage/*.elf
+*.elf.memfile
+sim/*Cache.log
+sim/branch
+tests/fp/combined_IF_vectors/IF_vectors/*.tv

.gitmodules

@@ -17,9 +17,10 @@
 [submodule "addins/embench-iot"]
 	path = addins/embench-iot
 	url = https://github.com/embench/embench-iot
-[submodule "addins/sky130_osu_sc_t18"]
-	path = addins/sky130_osu_sc_t18
-	url = https://foss-eda-tools.googlesource.com/skywater-pdk/libs/sky130_osu_sc_t18
-[submodule "addins/sky130_osu_sc_t12"]
-	path = addins/sky130_osu_sc_t12
-	url = https://foss-eda-tools.googlesource.com/skywater-pdk/libs/sky130_osu_sc_t12
+	branch = embench-1.0-branch
+[submodule "addins/coremark"]
+	path = addins/coremark
+	url = https://github.com/eembc/coremark
+[submodule "addins/branch-predictor-simulator"]
+	path = addins/branch-predictor-simulator
+	url = https://github.com/synxlin/branch-predictor-simulator.git

CONTRIBUTING.md

@@ -0,0 +1,24 @@
+<!---
+SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
+--->
+# Contributing
+New Contributors are always welcome.
+
+## Contributor Agreement
+Most Contributors are [members](https://www.openhwgroup.org/membership/) of the
+OpenHW Group and participate in one or more [Technical Task Groups](https://www.openhwgroup.org/working-groups/).
+Membership is strongly encouraged, but not required.  Contributors must be
+covered by the terms of the [Eclipse Contributor Agreement](https://www.eclipse.org/legal/ECA.php)
+(for individuals) **or** the [Eclipse Member Committer and Contributor Agreement](https://www.eclipse.org/legal/committer_process/EclipseMemberCommitterAgreement.pdf)
+(for employees of Member companies). The ECA/MCCA provides a legal
+framework for a Contributor's technical contributions to the OpenHW Group,
+including provisions for grant of copyright license and a Developer
+Certificate of Origin on contributions merged into OpenHW Group repositories.
+
+## The Mechanics
+1. [Fork](https://help.github.com/articles/fork-a-repo/) the [cvw](https://github.com/openhwgroup/cvw) repository
+2. Clone repository: `git clone https://github.com/[your_github_username]/cvw`
+3. Create your feature branch: `git checkout -b <my_branch>.`<br> Please uniquify your branch name.  See the [Git Cheats](https://github.com/openhwgroup/core-v-verif/blob/master/GitCheats.md) for a useful nominclature.
+5. Commit your changes: `git commit -m 'Add some feature'`
+6. Push feature branch: `git push origin <my_branch>`
+7. Submit a [pull request](https://help.github.com/en/github/collaborating-with-issues-and-pull-requests/creating-a-pull-request-from-a-fork).

LICENSE

@@ -1,22 +1,14 @@
-MIT License
-
-Copyright (c) 2021 Harvey Mudd College & Oklahoma State University
-Contact: Prof. David Harris  David_Harris@hmc.edu
-
-Permission is hereby granted, free of charge, to any person obtaining a copy
-of this software and associated documentation files (the "Software"), to deal
-in the Software without restriction, including without limitation the rights
-to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-copies of the Software, and to permit persons to whom the Software is
-furnished to do so, subject to the following conditions:
-
-The above copyright notice and this permission notice shall be included in all
-copies or substantial portions of the Software.
-
-THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
-OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-SOFTWARE.
+// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
+//
+// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
+//
+// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
+// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
+// may obtain a copy of the License at
+//
+// https://solderpad.org/licenses/SHL-2.1/
+//
+// Unless required by applicable law or agreed to in writing, any work distributed under the 
+// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
+// either express or implied. See the License for the specific language governing permissions 
+// and limitations under the License.

Makefile

@@ -1,22 +1,26 @@
+# David_Harris@hmc.edu 2023
+# Top-level Makefile for CORE-V-Wally
+# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
+
 all:
 	make install
 	make regression
 
 # install copies over the Makefile.include from riscv-isa-sim
-# And corrects the TARGETDIR path and the RISCV_PREFIXZ
+# And corrects the TARGETDIR path and the RISCV_PREFIX
 
 install:
-	cp ${RISCV}/riscv-isa-sim/arch_test_target/spike/Makefile.include addins/riscv-arch-test/
-	sed -i '/export TARGETDIR ?=/c\export TARGETDIR ?= ${RISCV}/riscv-isa-sim/arch_test_target' addins/riscv-arch-test/Makefile.include
-	echo export RISCV_PREFIX = riscv64-unknown-elf- >> addins/riscv-arch-test/Makefile.include
-	cd tests/linux-testgen/linux-testvectors; source ./tvLinker.sh # needs to be run in local directory
-	rm tests/imperas-riscv-tests/riscv-ovpsim-plus/bin/Linux64/riscvOVPsimPlus.exe
-	ln -s ${RISCV}/imperas-riscv-tests/riscv-ovpsim-plus/bin/Linux64/riscvOVPsimPlus.exe tests/imperas-riscv-tests/riscv-ovpsim-plus/bin/Linux64/riscvOVPsimPlus.exe
+	# *** 1/15/23 dh: check if any of this is still needed
+	#cp ${RISCV}/riscv-isa-sim/arch_test_target/spike/Makefile.include addins/riscv-arch-test/
+	#sed -i '/export TARGETDIR ?=/c\export TARGETDIR ?= ${RISCV}/riscv-isa-sim/arch_test_target' addins/riscv-arch-test/Makefile.include
+	#echo export RISCV_PREFIX = riscv64-unknown-elf- >> addins/riscv-arch-test/Makefile.include
+	##cd tests/linux-testgen/linux-testvectors; source ./tvLinker.sh # needs to be run in local directory
+	##rm tests/imperas-riscv-tests/riscv-ovpsim-plus/bin/Linux64/riscvOVPsimPlus.exe
+	##ln -s ${RISCV}/imperas-riscv-tests/riscv-ovpsim-plus/bin/Linux64/riscvOVPsimPlus.exe tests/imperas-riscv-tests/riscv-ovpsim-plus/bin/Linux64/riscvOVPsimPlus.exe
 
 regression:
-	make -C pipelined/regression
+	make -C sim
 
 clean:
-	make clean -C pipelined/regression
-	
+	make clean -C sim
 

README.md

@@ -1,33 +1,131 @@
-# riscv-wally
-Configurable RISC-V Processor
+# core-v-wally
 
-Wally is a 5-stage pipelined processor configurable to support all the standard RISC-V options, incluidng RV32/64, A, C, F, D, and M extensions, FENCE.I, and the various privileged modes and CSRs.  It is written in SystemVerilog.  It passes the RISC-V Arch Tests and Imperas tests.  As of October 2021, it boots the first 10 million instructions of Buildroot Linux.
+Wally is a 5-stage pipelined processor configurable to support all the standard RISC-V options, incluidng RV32/64, A, C, F, D, Q, M, and Zb* extensions, virtual memory, PMP, and the various privileged modes and CSRs. It provides optional caches, branch prediction, and standard RISC-V peripherals (CLINT, PLIC, UART, GPIO).   Wally is written in SystemVerilog.  It passes the RISC-V Arch Tests and boots Linux on an FPGA.  Configurations range from a minimal RV32E core to a fully featured RV64GC application processor.
 
-If you are new to using Linux and Github, follow the steps in the RISCV SoC Design textbook to:
+![Wally block diagram](wallyriscvTopAll.png)
 
+Wally is described in an upcoming textbook, *RISC-V System-on-Chip Design*, by Harris, Stine, Thompson, and Harris.  Users should follow the setup instructions below.  A system administrator must install CAD tools using the directions further down.
 
-See Chapter 2 of draft book of how to install and compile tests.
+# Verification
 
-	Download and install x2go - A.1
-	Download and install VSCode - A.4.2
-	Make sure you can log into Tera acceptly via x2go and via a terminal
+Wally is presently at Technology Readiness Level 4, passing the RISC-V compatibility test suite and custom tests, and booting Linux in simulation and on an FPGA.  See the [Test Plan](docs/testplan.md) for details.
+
+# New User Setup
+
+New users may wish to do the following setup to access the server via a GUI and use a text editor.
+
+	Git started with Git configuration and authentication: B.1 (replace with your name and email)
+		$ git config --global user.name "Ben Bitdiddle"
+		$ git config --global user.email "ben_bitdiddle@wally.edu"
+		$ git config --global pull.rebase false
+	Optional: Download and install x2go - A.1.1
+	Optional: Download and install VSCode - A.4.2
+	Optional: Make sure you can log into your server via x2go and via a terminal
 		Terminal on Mac, cmd on Windows, xterm on Linux
 		See A.1 about ssh -Y login from a terminal
-	Git started with Git configuration and authentication: B.1
 
-Then follow Section 2.2.2 to clone the repo, source setup,  make the tests and run regression
+Then clone the repo, source setup,  make the tests and run regression
+
+	If you don't already have a Github account, create one
+	In a web browser, visit https://github.com/openhwgroup/cvw
+	In the upper right part of the screen, click on Fork
+	Create a fork, choosing the owner as your github account and the repository as cvw.
+	
+	On the Linux computer where you will be working, log in
+
+Clone your fork of the repo and run the setup script. Change <yourgithubid> to your github id. 
 
 	$ cd
-	$ export RISCV=/opt/riscv
-	$ git clone --recurse-submodules https://github.com/davidharrishmc/riscv-wally
-	$ cd riscv-wally
+	$ git clone --recurse-submodules https://github.com/<yourgithubid>/cvw
+	$ cd cvw
+	$ git remote add upstream https://github.com/openhwgroup/cvw
 	$ source ./setup.sh
+
+Add the following lines to your .bashrc or .bash_profile to run the setup script each time you log in.
+
+	if [ -f ~/cvw/setup.sh ]; then
+		source ~/cvw/setup.sh
+	fi
+
+Edit setup.sh and change the following lines to point to the path and license server for your Siemens Questa and Synopsys Design Compiler installation and license server.  If you only have Questa, you can still simulate but cannot run logic synthesis.
+
+	export MGLS_LICENSE_FILE=1717@solidworks.eng.hmc.edu                # Change this to your Siemens license server
+	export SNPSLMD_LICENSE_FILE=27020@zircon.eng.hmc.edu                # Change this to your Synopsys license server
+	export QUESTAPATH=/cad/mentor/questa_sim-2021.2_1/questasim/bin     # Change this for your path to Questa
+	export SNPSPATH=/cad/synopsys/SYN/bin                               # Change this for your path to Design Compiler
+
+If the tools are not yet installed on your server, follow the Toolchain Installation instructions in the section below.
+
+Build the tests and run a regression simulation with Questa to prove everything is installed.  Building tests will take a while.
+
 	$ make
-	$ cd pipelined/regression
+	$ cd sim
 	$ ./regression-wally       (depends on having Questa installed)
 
-Add the following lines to your .bashrc or .bash_profile
+# Toolchain Installation (Sys Admin)
+
+This section describes the open source toolchain installation.  The
+current version of the toolchain has been tested on Ubuntu and Red
+Hat/Rocky 8 Linux.  Ubuntu works more smoothly and is recommended
+unless you have a compelling need for RedHat.  
+
+Ubuntu users can install the tools by running
+
+	$ sudo $WALLY/bin/wally-tool-chain-install.sh
+
+See wally-tool-chain-install.sh for a detailed description of each component,
+or to issue the commands one at a time to install on the command line.
+## Installing EDA Tools
+
+Electronic Design Automation (EDA) tools are vital to implementations of System on Chip architectures as well as validating different designs.   Open-source and commercial tools exist for multiple strategies and although the one can spend a lifetime using combinations of different tools, only a small subset of tools is utilized for this text.  The tools are chosen because of their ease in access as well as their repeatability for accomplishing many of the tasks utilized to design Wally.  It is anticipated that additional tools may be documented later after this is text is published to improve use and access.
+
+Siemens Quest is the primary tool utilized for simulating and validating Wally.    For logic synthesis, you will need Synopsys Design Compiler.  Questa and Design Compiler are commercial tools that require an educational or commercial license.  
+
+Note: Some EDA tools utilize LM_LICENSE_FILE for their environmental variable to point to their license server.  Some operating systems may also utilize MGLS_LICENSE_FILE instead, therefore, it is important to read the user manual on the preferred environmental variable required to point to a user’s license file.  Although there are different mechanisms to allow licenses to work, many companies commonly utilize the FlexLM (i.e., Flex-enabled) license server manager that runs off a node locked license.
+
+Although most EDA tools are Linux-friendly, they tend to have issues when not installed on recommended OS flavors.  Both Red Hat Enterprise Linux and SUSE Linux products typically tend to be recommended for installing commercial-based EDA tools and are recommended for utilizing complex simulation and architecture exploration.  Questa can also be installed on Microsoft Windows as well as Mac OS with a Virtual Machine such as Parallels.  
+
+Siemens Questa
+
+Siemens Questa simulates behavioral, RTL and gate-level HDL.  To install Siemens Questa first go to a web browser and navigate to 
+https://eda.sw.siemens.com/en-US/ic/questa/simulation/advanced-simulator/.  Click Sign In and log in with your credentials and the product can easily be downloaded and installed.  Some  Windows-based installations also require gcc libraries that are typically provided as a compressed zip download through Siemens.  
+
+Synopsys Design Compiler (DC)
+
+Many commercial synthesis and place and route tools require a common installer.  These installers are provided by the EDA vendor and Synopsys has one called Synopsys Installer.  To use Synopsys Installer, you will need to acquire a license through Synopsys that is typically Called Synopsys Common Licensing (SCL).  Both the Synopsys Installer, license key file, and Design Compiler can all be downloaded through Synopsys Solvnet.  First open a web browser, log into Synsopsy Solvnet, and download the installer and Design Compiler installation files.  Then, install the Installer
+
+	$ firefox &
+Navigate to https://solvnet.synopsys.com
+Log in with your institution’s username and password
+Click on Downloads, then scroll down to Synopsys Installer
+Select the latest version (currently 5.4).  Click Download Here, agree,
+Click on SynopsysInstaller_v5.4.run
+Return to downloads and also get Design Compiler (synthesis) latest version, and any others you want.
+	Click on all parts and the .spf file, then click Download Files near the top
+move the SynopsysIntaller into /cad/synopsys/Installer_5.4 with 755 permission for cad, 
+move other files into /cad/synopsys/downloads and work as user cad from here on
+
+	$ cd /cad/synopsys/installer_5.4
+	$ ./SynopsysInstaller_v5.4.run
+	Accept default installation directory
+	$ ./installer
+	Enter source path as /cad/synopsys/downloads, and installation path as /cad/synopsys
+	When prompted, enter your site ID
+	Follow prompts
+
+Installer can be utilized in graphical or text-based modes.  It is far easier to use the text-based installation tool.  To install DC, navigate to the location where your downloaded DC files are and type installer.  You should be prompted with questions related to where you wish to have your files installed.  
+
+The Synopsys Installer automatically installs all downloaded product files into a single top-level target directory. You do not need to specify the installation directory for each product. For example, if you specify /import/programs/synopsys as the target directory, your installation directory structure might look like this after installation:
+
+	/import/programs/synopsys/syn/S-2021.06-SP1
+
+Note: Although most parts of Wally, including the software used in this chapter and Questa simulation, will work on most modern Linux platforms, as of 2022, the Synopsys CAD tools for SoC design are only supported on RedHat Enterprise Linux 7.4 or 8 or SUSE Linux Enterprise Server (SLES) 12 or 15. Moreover, the RISC-V formal specification (sail-riscv) does not build gracefully on RHEL7. 
+
+The Verilog simulation has been tested with Siemens Questa/ModelSim. This package is available to universities worldwide as part of the Design Verification Bundle through the Siemens Academic Partner Program members for $990/year. 
+
+If you want to implement your own version of the chip, your tool and license complexity rises significantly. Logic synthesis uses Synopsys Design Compiler. Placement and routing uses Cadence Innovus. Both Synopsys and Cadence offer their tools at a steep discount to their university program members, but the cost is still several thousand dollars per year. Most research universities with integrated circuit design programs have Siemens, Synopsys, and Cadence licenses. You also need a process design kit (PDK) for a specific integrated circuit technology and its libraries. The open-source Google Skywater 130 nm PDK is sufficient to synthesize the core but lacks memories. Google presently funds some fabrication runs for universities. IMEC and Muse Semiconductor offers full access to multiproject wafer fabrication on the TSMC 28 nm process including logic, I/O, and memory libraries; this involves three non-disclosure agreements. Fabrication costs on the order of $10,000 for a batch of 1 mm2 chips. 
+
+Startups can expect to spend more than $1 million on CAD tools to get a chip to market. Commercial CAD tools are not realistically available to individuals without a university or company connection.
+
+
 
-	if [ -f ~/riscv-wally/setup.sh ]; then
-		source ~/riscv-wally/setup.sh
-	fi