forked from Github_Repos/cvw
Switched csri IP_REGW to use assignements rather than always_comb as this is incompatible with forcing.
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@ -95,21 +95,20 @@ module csri #(parameter
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// else if (WriteUIEM) IE_REGW = (CSRWriteValM & 12'h111) | (IE_REGW & 12'hAAA); // only U field
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// restricted views of registers
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always_comb begin:regs
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// Add MEIP read-only signal
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IP_REGW = {IntInM[11],1'b0,IP_REGW_writeable};
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// Add MEIP read-only signal
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assign IP_REGW = {IntInM[11],1'b0,IP_REGW_writeable};
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// Machine Mode
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MIP_REGW = IP_REGW;
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MIE_REGW = IE_REGW;
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assign MIP_REGW = IP_REGW;
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assign MIE_REGW = IE_REGW;
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// Supervisor mode
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if (`S_SUPPORTED) begin
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SIP_REGW = IP_REGW & MIDELEG_REGW[11:0] & 'h222; // only delegated interrupts visible
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SIE_REGW = IE_REGW & MIDELEG_REGW[11:0] & 'h222;
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end else begin
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SIP_REGW = 12'b0;
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SIE_REGW = 12'b0;
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end
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// Supervisor mode
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if (`S_SUPPORTED) begin
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assign SIP_REGW = IP_REGW & MIDELEG_REGW[11:0] & 'h222; // only delegated interrupts visible
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assign SIE_REGW = IE_REGW & MIDELEG_REGW[11:0] & 'h222;
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end else begin
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assign SIP_REGW = 12'b0;
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assign SIE_REGW = 12'b0;
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end
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endmodule
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