forked from Github_Repos/cvw
added SIP, SIE, and SSTATUS to checkpoints. Can't seem to get the linux testbench to force SIP.
This commit is contained in:
Ross Thompson
parent
e6b42cb10f
commit
4ca9458534
@ -138,9 +138,9 @@ if len(sys.argv) != 2:
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sys.exit('Error parseGDBtoTrace.py expects 1 arg:\n <interrupt filename>>')
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interruptFname = sys.argv[1]
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# reg number
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RegNumber = {'zero': 0, 'ra': 1, 'sp': 2, 'gp': 3, 'tp': 4, 't0': 5, 't1': 6, 't2': 7, 's0': 8, 's1': 9, 'a0': 10, 'a1': 11, 'a2': 12, 'a3': 13, 'a4': 14, 'a5': 15, 'a6': 16, 'a7': 17, 's2': 18, 's3': 19, 's4': 20, 's5': 21, 's6': 22, 's7': 23, 's8': 24, 's9': 25, 's10': 26, 's11': 27, 't3': 28, 't4': 29, 't5': 30, 't6': 31, 'mhartid': 32, 'mstatus': 33, 'mip': 34, 'mie': 35, 'mideleg': 36, 'medeleg': 37, 'mtvec': 38, 'stvec': 39, 'mepc': 40, 'sepc': 41, 'mcause': 42, 'scause': 43, 'mtval': 44, 'stval': 45}
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RegNumber = {'zero': 0, 'ra': 1, 'sp': 2, 'gp': 3, 'tp': 4, 't0': 5, 't1': 6, 't2': 7, 's0': 8, 's1': 9, 'a0': 10, 'a1': 11, 'a2': 12, 'a3': 13, 'a4': 14, 'a5': 15, 'a6': 16, 'a7': 17, 's2': 18, 's3': 19, 's4': 20, 's5': 21, 's6': 22, 's7': 23, 's8': 24, 's9': 25, 's10': 26, 's11': 27, 't3': 28, 't4': 29, 't5': 30, 't6': 31, 'mhartid': 32, 'mstatus': 33, 'mip': 34, 'mie': 35, 'mideleg': 36, 'medeleg': 37, 'mtvec': 38, 'stvec': 39, 'mepc': 40, 'sepc': 41, 'mcause': 42, 'scause': 43, 'mtval': 44, 'stval': 45, 'sstatus': 46, 'sip': 47, 'sie': 48}
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# initial state
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CurrentInstr = ['0', '0', None, 'other', {'zero': 0, 'ra': 0, 'sp': 0, 'gp': 0, 'tp': 0, 't0': 0, 't1': 0, 't2': 0, 's0': 0, 's1': 0, 'a0': 0, 'a1': 0, 'a2': 0, 'a3': 0, 'a4': 0, 'a5': 0, 'a6': 0, 'a7': 0, 's2': 0, 's3': 0, 's4': 0, 's5': 0, 's6': 0, 's7': 0, 's8': 0, 's9': 0, 's10': 0, 's11': 0, 't3': 0, 't4': 0, 't5': 0, 't6': 0, 'mhartid': 0, 'mstatus': 0, 'mip': 0, 'mie': 0, 'mideleg': 0, 'medeleg': 0, 'mtvec': 0, 'stvec': 0, 'mepc': 0, 'sepc': 0, 'mcause': 0, 'scause': 0, 'mtval': 0, 'stval': 0}, {}, None, None, None]
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CurrentInstr = ['0', '0', None, 'other', {'zero': 0, 'ra': 0, 'sp': 0, 'gp': 0, 'tp': 0, 't0': 0, 't1': 0, 't2': 0, 's0': 0, 's1': 0, 'a0': 0, 'a1': 0, 'a2': 0, 'a3': 0, 'a4': 0, 'a5': 0, 'a6': 0, 'a7': 0, 's2': 0, 's3': 0, 's4': 0, 's5': 0, 's6': 0, 's7': 0, 's8': 0, 's9': 0, 's10': 0, 's11': 0, 't3': 0, 't4': 0, 't5': 0, 't6': 0, 'mhartid': 0, 'mstatus': 0, 'mip': 0, 'mie': 0, 'mideleg': 0, 'medeleg': 0, 'mtvec': 0, 'stvec': 0, 'mepc': 0, 'sepc': 0, 'mcause': 0, 'scause': 0, 'mtval': 0, 'stval': 0, 'sstatus': 0, 'sip': 0, 'sie': 0}, {}, None, None, None]
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#with open (InputFile, 'r') as InputFileFP:
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#lines = InputFileFP.readlines()
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@ -34,7 +34,7 @@ stateGDBpath = outDir+'stateGDB.txt'
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if not os.path.exists(stateGDBpath):
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sys.exit('Error input file '+stateGDBpath+'not found')
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singleCSRs = ['pc','mip','mie','mscratch','mcause','mepc','mtvec','medeleg','mideleg','sscratch','scause','sepc','stvec','sedeleg','sideleg','satp','mstatus','priv']
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singleCSRs = ['pc','mip','mie','mscratch','mcause','mepc','mtvec','medeleg','mideleg','sscratch','scause','sepc','stvec','sedeleg','sideleg','satp','mstatus','priv','sie','sip','sstatus']
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# priv (current privilege mode) isn't technically a CSR but we can log it with the same machinery
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thirtyTwoBitCSRs = ['mcounteren','scounteren']
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listCSRs = ['hpmcounter','pmpaddr']
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@ -141,11 +141,11 @@ module testbench;
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logic [`XLEN-1:0] ExpectedCSRArrayValue``STAGE[10:0];
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`DECLARE_TRACE_SCANNER_SIGNALS(E)
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`DECLARE_TRACE_SCANNER_SIGNALS(M)
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integer NextMIPexpected;
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integer NextMIPexpected, NextSIPexpected;
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integer NextMepcExpected;
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// Memory stage expected values from trace
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logic checkInstrM;
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integer MIPexpected;
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integer MIPexpected, SIPexpected;
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string name;
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logic [`AHBW-1:0] readDataExpected;
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// Write back stage expected values from trace
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@ -168,11 +168,14 @@ module testbench;
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integer NumCSRPostWIndex;
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logic [`XLEN-1:0] InstrCountW;
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integer RequestDelayedMIP;
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integer RequestDelayedSIP;
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integer ForceMIPFuture;
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integer CSRIndex;
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longint MepcExpected;
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integer CheckMIPFutureE;
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integer CheckMIPFutureM;
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integer CheckSIPFutureE;
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integer CheckSIPFutureM;
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// Useful Aliases
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`define RF dut.core.ieu.dp.regf.rf
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`define PC dut.core.ifu.pcreg.q
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@ -185,6 +188,8 @@ module testbench;
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`define MIDELEG `CSR_BASE.csrm.deleg.MIDELEGreg.q
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`define MIE `CSR_BASE.csri.MIE_REGW
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`define MIP `CSR_BASE.csri.MIP_REGW
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`define SIE `CSR_BASE.csri.SIE_REGW
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`define SIP `CSR_BASE.csri.SIP_REGW
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`define MCAUSE `CSR_BASE.csrm.MCAUSEreg.q
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`define SCAUSE `CSR_BASE.csrs.csrs.SCAUSEreg.q
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`define MEPC `CSR_BASE.csrm.MEPCreg.q
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@ -197,6 +202,7 @@ module testbench;
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`define STVEC `CSR_BASE.csrs.csrs.STVECreg.q
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`define SATP `CSR_BASE.csrs.csrs.genblk1.SATPreg.q
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`define MSTATUS `CSR_BASE.csrsr.MSTATUS_REGW
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`define SSTATUS `CSR_BASE.csrsr.SSTATUS_REGW
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`define STATUS_TSR `CSR_BASE.csrsr.STATUS_TSR_INT
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`define STATUS_TW `CSR_BASE.csrsr.STATUS_TW_INT
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`define STATUS_TVM `CSR_BASE.csrsr.STATUS_TVM_INT
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@ -297,6 +303,8 @@ module testbench;
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`INIT_CHECKPOINT_VAL(MIDELEG, [`XLEN-1:0]);
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`INIT_CHECKPOINT_VAL(MIE, [11:0]);
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`INIT_CHECKPOINT_VAL(MIP, [11:0]);
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`INIT_CHECKPOINT_VAL(SIE, [11:0]);
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`INIT_CHECKPOINT_VAL(SIP, [11:0]);
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`INIT_CHECKPOINT_VAL(MCAUSE, [`XLEN-1:0]);
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`INIT_CHECKPOINT_VAL(SCAUSE, [`XLEN-1:0]);
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`INIT_CHECKPOINT_VAL(MEPC, [`XLEN-1:0]);
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@ -310,6 +318,7 @@ module testbench;
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`INIT_CHECKPOINT_VAL(SATP, [`XLEN-1:0]);
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`INIT_CHECKPOINT_VAL(PRIV, [1:0]);
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`MAKE_CHECKPOINT_INIT_SIGNAL(MSTATUS, [`XLEN-1:0],0,0);
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`MAKE_CHECKPOINT_INIT_SIGNAL(SSTATUS, [`XLEN-1:0],0,0);
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// Many UART registers are difficult to initialize because under the hood
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// they are not simple registers. Instead some are generated by interesting
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// combinational blocks such that they depend upon a variety of different
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@ -463,6 +472,10 @@ module testbench;
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CheckMIPFutureE = 1; \
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NextMIPexpected = ExpectedCSRArrayValueE[NumCSRE]; \
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end \
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if(ExpectedCSRArrayE[NumCSRE].substr(0, 2) == "sip") begin \
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CheckSIPFutureE = 1; \
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NextSIPexpected = ExpectedCSRArrayValueE[NumCSRE]; \
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end \
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if(ExpectedCSRArrayE[NumCSRE].substr(0,3) == "mepc") begin \
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// $display("hello! we are here."); \
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MepcExpected = ExpectedCSRArrayValueE[NumCSRE]; \
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@ -501,6 +514,7 @@ module testbench;
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if(CheckMIPFutureE) CheckMIPFutureE <= 0;
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CheckMIPFutureM <= CheckMIPFutureE;
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if(CheckMIPFutureM) begin
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$display("DEBUG DEBUG DEBUG DEBUG");
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// $display("%tns: ExpectedPCM %x",$time,ExpectedPCM);
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// $display("%tns: ExpectedPCE %x",$time,ExpectedPCE);
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// $display("%tns: ExpectedPCW %x",$time,ExpectedPCW);
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@ -508,9 +522,12 @@ module testbench;
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RequestDelayedMIP <= 1;
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$display("%tns: Requesting Delayed MIP. Current MEPC value is %x",$time,MepcExpected);
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end else begin // update MIP immediately
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$display("One One One One");
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$display("%tns: Updating MIP to %x",$time,NextMIPexpected);
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MIPexpected = NextMIPexpected;
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force dut.core.priv.priv.csr.csri.MIP_REGW = MIPexpected;
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//force dut.core.priv.priv.csr.csri.MIP_REGW = MIPexpected;
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//force dut.core.priv.priv.csr.csri.SIP_REGW = MIPexpected;
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force dut.core.priv.priv.csr.csri.IP_REGW = MIPexpected;
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end
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// $display("%tn: ExpectedCSRArrayM = %p",$time,ExpectedCSRArrayM);
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// $display("%tn: ExpectedCSRArrayValueM = %p",$time,ExpectedCSRArrayValueM);
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@ -524,13 +541,54 @@ module testbench;
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if(RequestDelayedMIP & checkInstrM) begin
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$display("%tns: Executing Delayed MIP. Current MEPC value is %x",$time,dut.core.priv.priv.csr.csrm.MEPC_REGW);
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$display("%tns: Updating MIP to %x",$time,NextMIPexpected);
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$display("Two Two Two Two");
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MIPexpected = NextMIPexpected;
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force dut.core.priv.priv.csr.csri.MIP_REGW = MIPexpected;
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//force dut.core.priv.priv.csr.csri.MIP_REGW = MIPexpected;
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//force dut.core.priv.priv.csr.csri.SIP_REGW = MIPexpected;
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force dut.core.priv.priv.csr.csri.IP_REGW = MIPexpected;
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$display("%tns: Finished Executing Delayed MIP. Current MEPC value is %x",$time,dut.core.priv.priv.csr.csrm.MEPC_REGW);
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RequestDelayedMIP = 0;
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end
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end
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// SIP spoofing
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/* -----\/----- EXCLUDED -----\/-----
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always @(posedge clk) begin
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#1;
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if(CheckSIPFutureE) CheckSIPFutureE <= 0;
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CheckSIPFutureM <= CheckSIPFutureE;
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if(CheckSIPFutureM) begin
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// $display("%tns: ExpectedPCM %x",$time,ExpectedPCM);
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// $display("%tns: ExpectedPCE %x",$time,ExpectedPCE);
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// $display("%tns: ExpectedPCW %x",$time,ExpectedPCW);
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if((ExpectedPCE != MepcExpected) & ((MepcExpected - ExpectedPCE) * (MepcExpected - ExpectedPCE) <= 200) | ~dut.core.ieu.c.InstrValidM) begin
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RequestDelayedSIP <= 1;
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$display("%tns: Requesting Delayed SIP. Current MEPC value is %x",$time,MepcExpected);
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end else begin // update SIP immediately
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$display("%tns: Updating SIP to %x",$time,NextSIPexpected);
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SIPexpected = NextSIPexpected;
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force dut.core.priv.priv.csr.csri.SIP_REGW = SIPexpected;
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end
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// $display("%tn: ExpectedCSRArrayM = %p",$time,ExpectedCSRArrayM);
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// $display("%tn: ExpectedCSRArrayValueM = %p",$time,ExpectedCSRArrayValueM);
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// $display("%tn: ExpectedTokens = %p",$time,ExpectedTokensM);
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// $display("%tn: MepcExpected = %x",$time,MepcExpected);
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// $display("%tn: ExpectedPCE = %x",$time,ExpectedPCE);
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// $display("%tns: Difference/multiplication thing: %x",$time,(MepcExpected - ExpectedPCE) * (MepcExpected - ExpectedPCE));
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// $display("%tn: ExpectedCSRArrayM[NumCSRM] %x",$time,ExpectedCSRArrayM[NumCSRM]);
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// $display("%tn: ExpectedCSRArrayValueM[NumCSRM] %x",$time,ExpectedCSRArrayValueM[NumCSRM]);
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end
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if(RequestDelayedSIP & checkInstrM) begin
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$display("%tns: Executing Delayed SIP. Current MEPC value is %x",$time,dut.core.priv.priv.csr.csrm.MEPC_REGW);
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$display("%tns: Updating SIP to %x",$time,NextSIPexpected);
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SIPexpected = NextSIPexpected;
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force dut.core.priv.priv.csr.csri.SIP_REGW = SIPexpected;
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$display("%tns: Finished Executing Delayed SIP. Current MEPC value is %x",$time,dut.core.priv.priv.csr.csrm.MEPC_REGW);
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RequestDelayedSIP = 0;
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end
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end
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-----/\----- EXCLUDED -----/\----- */
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// step 1: register expected state into the write back stage.
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always @(posedge clk) begin
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if (reset) begin
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@ -634,9 +692,12 @@ module testbench;
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case(ExpectedCSRArrayW[NumCSRPostWIndex])
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"mhartid": `checkCSR(dut.core.priv.priv.csr.csrm.MHARTID_REGW)
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"mstatus": `checkCSR(dut.core.priv.priv.csr.csrm.MSTATUS_REGW)
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"sstatus": `checkCSR(dut.core.priv.priv.csr.csrs.SSTATUS_REGW)
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"mtvec": `checkCSR(dut.core.priv.priv.csr.csrm.MTVEC_REGW)
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"mip": `checkCSR(dut.core.priv.priv.csr.csrm.MIP_REGW)
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"mie": `checkCSR(dut.core.priv.priv.csr.csrm.MIE_REGW)
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"sip": `checkCSR(dut.core.priv.priv.csr.csrs.SIP_REGW)
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"sie": `checkCSR(dut.core.priv.priv.csr.csrs.SIE_REGW)
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"mideleg": `checkCSR(dut.core.priv.priv.csr.csrm.MIDELEG_REGW)
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"medeleg": `checkCSR(dut.core.priv.priv.csr.csrm.MEDELEG_REGW)
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"mepc": `checkCSR(dut.core.priv.priv.csr.csrm.MEPC_REGW)
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