forked from Github_Repos/cvw
Merge branch 'main' of https://github.com/openhwgroup/cvw
This commit is contained in:
Ross Thompson
commit
17f80285ca
@ -114,6 +114,8 @@ module controller(
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logic SFenceVmaD; // sfence.vma instruction
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logic IntDivM; // Integer divide instruction
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logic IFunctD, RFunctD, MFunctD; // Detect I, R, and M-type RV32IM/Rv64IM instructions
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logic LFunctD, SFunctD, BFunctD; // Detect load, store, branch instructions
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logic JFunctD; // detect jalr instruction
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// Extract fields
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assign OpD = InstrD[6:0];
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@ -125,28 +127,43 @@ module controller(
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// Be rigorous about detecting illegal instructions if CSRs or bit manipulation is supported
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// otherwise be cheap
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if (`ZICSR_SUPPORTED | `ZBA_SUPPORTED | `ZBB_SUPPORTED | `ZBC_SUPPORTED | `ZBS_SUPPORTED) begin // Exact integer decoding
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if (`ZICSR_SUPPORTED | `ZBA_SUPPORTED | `ZBB_SUPPORTED | `ZBC_SUPPORTED | `ZBS_SUPPORTED) begin:legalcheck // Exact integer decoding
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logic Funct7ZeroD, Funct7b5D, IShiftD, INoShiftD;
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logic Funct7ShiftZeroD, Funct7Shiftb5D;
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assign Funct7ZeroD = (Funct7D == 7'b0000000); // most R-type instructions
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assign Funct7b5D = (Funct7D == 7'b0100000); // srai, sub
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assign IShiftD = (Funct3D == 3'b001 & Funct7ZeroD) | (Funct3D == 3'b101 & (Funct7ZeroD | Funct7b5D)); // slli, srli, srai, or w forms
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assign INoShiftD = (Funct3D != 3'b001 & Funct3D != 3'b101);
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assign Funct7ShiftZeroD = (`XLEN==64) ? (Funct7D[6:1] == 6'b000000) : Funct7ZeroD;
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assign Funct7Shiftb5D = (`XLEN==64) ? (Funct7D[6:1] == 6'b010000) : Funct7b5D;
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assign IShiftD = (Funct3D == 3'b001 & Funct7ShiftZeroD) | (Funct3D == 3'b101 & (Funct7ShiftZeroD | Funct7Shiftb5D)); // slli, srli, srai, or w forms
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assign INoShiftD = ((Funct3D != 3'b001) & (Funct3D != 3'b101));
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assign IFunctD = IShiftD | INoShiftD;
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assign RFunctD = ((Funct3D == 3'b000 | Funct3D == 3'b101) & Funct7b5D) | Funct7ZeroD;
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assign MFunctD = (Funct7D == 7'b0000001) & (`M_SUPPORTED | (`ZMMUL_SUPPORTED & ~Funct3D[2])); // muldiv
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end else begin
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assign LFunctD = Funct3D == 3'b000 | Funct3D == 3'b001 | Funct3D == 3'b010 | Funct3D == 3'b100 | Funct3D == 3'b101 |
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((`XLEN == 64) & (Funct3D == 3'b011 | Funct3D == 3'b110));
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assign SFunctD = Funct3D == 3'b000 | Funct3D == 3'b001 | Funct3D == 3'b010 |
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((`XLEN == 64) & (Funct3D == 3'b011));
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assign BFunctD = (Funct3D[2:1] != 2'b01); // legal branches
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assign JFunctD = (Funct3D == 3'b000);
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end else begin:legalcheck2
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assign IFunctD = 1; // Don't bother to separate out shift decoding
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assign RFunctD = ~Funct7D[0]; // Not a multiply
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assign MFunctD = Funct7D[0] & (`M_SUPPORTED | (`ZMMUL_SUPPORTED & ~Funct3D[2])); // muldiv
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assign LFunctD = 1; // don't bother to check Funct3 for loads
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assign SFunctD = 1; // don't bother to check Funct3 for stores
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assign BFunctD = 1; // don't bother to check Funct3 for branches
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assign JFunctD = 1; // don't bother to check Funct3 for jumps
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end
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// Main Instruction Decoder
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always_comb
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/* verilator lint_off CASEINCOMPLETE */
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always_comb begin
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ControlsD = `CTRLW'b0_000_00_00_000_0_0_0_0_0_0_0_0_0_00_1; // default: Illegal instruction
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case(OpD)
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// RegWrite_ImmSrc_ALUSrc_MemRW_ResultSrc_Branch_ALUOp_Jump_ALUResultSrc_W64_CSRRead_Privileged_Fence_MDU_Atomic_Illegal
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7'b0000000: ControlsD = `CTRLW'b0_000_00_00_000_0_0_0_0_0_0_0_0_0_00_1; // Illegal instruction
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7'b0000011: ControlsD = `CTRLW'b1_000_01_10_001_0_0_0_0_0_0_0_0_0_00_0; // lw
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7'b0000011: if (LFunctD)
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ControlsD = `CTRLW'b1_000_01_10_001_0_0_0_0_0_0_0_0_0_00_0; // loads
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7'b0000111: ControlsD = `CTRLW'b0_000_01_10_001_0_0_0_0_0_0_0_0_0_00_1; // flw - only legal if FP supported
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7'b0001111: if (`ZIFENCEI_SUPPORTED)
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ControlsD = `CTRLW'b0_000_00_00_000_0_0_0_0_0_0_0_1_0_00_0; // fence
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@ -154,14 +171,11 @@ module controller(
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ControlsD = `CTRLW'b0_000_00_00_000_0_0_0_0_0_0_0_0_0_00_0; // fence treated as nop
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7'b0010011: if (IFunctD)
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ControlsD = `CTRLW'b1_000_01_00_000_0_1_0_0_0_0_0_0_0_00_0; // I-type ALU
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else
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ControlsD = `CTRLW'b0_000_00_00_000_0_0_0_0_0_0_0_0_0_00_1; // Non-implemented instruction
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7'b0010111: ControlsD = `CTRLW'b1_100_11_00_000_0_0_0_0_0_0_0_0_0_00_0; // auipc
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7'b0011011: if (IFunctD & `XLEN == 64)
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ControlsD = `CTRLW'b1_000_01_00_000_0_1_0_0_1_0_0_0_0_00_0; // IW-type ALU for RV64i
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else
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ControlsD = `CTRLW'b0_000_00_00_000_0_0_0_0_0_0_0_0_0_00_1; // Non-implemented instruction
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7'b0100011: ControlsD = `CTRLW'b0_001_01_01_000_0_0_0_0_0_0_0_0_0_00_0; // sw
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7'b0100011: if (SFunctD)
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ControlsD = `CTRLW'b0_001_01_01_000_0_0_0_0_0_0_0_0_0_00_0; // stores
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7'b0100111: ControlsD = `CTRLW'b0_001_01_01_000_0_0_0_0_0_0_0_0_0_00_1; // fsw - only legal if FP supported
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7'b0101111: if (`A_SUPPORTED) begin
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if (InstrD[31:27] == 5'b00010)
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@ -170,33 +184,30 @@ module controller(
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ControlsD = `CTRLW'b1_101_01_01_100_0_0_0_0_0_0_0_0_0_01_0; // sc
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else
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ControlsD = `CTRLW'b1_101_01_11_001_0_0_0_0_0_0_0_0_0_10_0; // amo
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end else
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ControlsD = `CTRLW'b0_000_00_00_000_0_0_0_0_0_0_0_0_0_00_1; // Non-implemented instruction
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end
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7'b0110011: if (RFunctD)
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ControlsD = `CTRLW'b1_000_00_00_000_0_1_0_0_0_0_0_0_0_00_0; // R-type
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else if (MFunctD)
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ControlsD = `CTRLW'b1_000_00_00_011_0_0_0_0_0_0_0_0_1_00_0; // Multiply/divide
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else
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ControlsD = `CTRLW'b0_000_00_00_000_0_0_0_0_0_0_0_0_0_00_1; // Non-implemented instruction
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7'b0110111: ControlsD = `CTRLW'b1_100_01_00_000_0_0_0_1_0_0_0_0_0_00_0; // lui
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7'b0111011: if (RFunctD & (`XLEN == 64))
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ControlsD = `CTRLW'b1_000_00_00_000_0_1_0_0_1_0_0_0_0_00_0; // R-type W instructions for RV64i
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else if (MFunctD & (`XLEN == 64))
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ControlsD = `CTRLW'b1_000_00_00_011_0_0_0_0_1_0_0_0_1_00_0; // W-type Multiply/Divide
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else
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ControlsD = `CTRLW'b0_000_00_00_000_0_0_0_0_0_0_0_0_0_00_1; // Non-implemented instruction
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7'b1100011: ControlsD = `CTRLW'b0_010_11_00_000_1_0_0_0_0_0_0_0_0_00_0; // branches
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7'b1100111: ControlsD = `CTRLW'b1_000_01_00_000_0_0_1_1_0_0_0_0_0_00_0; // jalr
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7'b1100011: if (BFunctD)
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ControlsD = `CTRLW'b0_010_11_00_000_1_0_0_0_0_0_0_0_0_00_0; // branches
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7'b1100111: if (JFunctD)
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ControlsD = `CTRLW'b1_000_01_00_000_0_0_1_1_0_0_0_0_0_00_0; // jalr
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7'b1101111: ControlsD = `CTRLW'b1_011_11_00_000_0_0_1_1_0_0_0_0_0_00_0; // jal
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7'b1110011: if (`ZICSR_SUPPORTED) begin
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if (Funct3D == 3'b000)
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ControlsD = `CTRLW'b0_000_00_00_000_0_0_0_0_0_0_1_0_0_00_0; // privileged; decoded further in priveleged modules
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else
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ControlsD = `CTRLW'b1_000_00_00_010_0_0_0_0_0_1_0_0_0_00_0; // csrs
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end else
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ControlsD = `CTRLW'b0_000_00_00_000_0_0_0_0_0_0_0_0_0_00_1; // non-implemented instruction
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default: ControlsD = `CTRLW'b0_000_00_00_000_0_0_0_0_0_0_0_0_0_00_1; // non-implemented instruction
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end
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endcase
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end
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/* verilator lint_on CASEINCOMPLETE */
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// Unswizzle control bits
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// Squash control signals if coming from an illegal compressed instruction
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