forked from Github_Repos/cvw
little fix
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@ -144,7 +144,7 @@ module srtpreproc (
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assign DivX = Int ? PreprocA : PreprocX;
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assign SqrtX = XExp[0] ? {4'b0000, SrcXFrac, 1'b0} : {5'b11111, SrcXFrac};
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assign X = Sqrt ? {SqrtX, {(`EXTRAINTBITS-1){1'b0}}} : {4'b0001, DivX};
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assign X = Sqrt ? {SqrtX, {(`EXTRAFRACBITS-1){1'b0}}} : {4'b0001, DivX};
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assign D = {4'b0001, Int ? PreprocB : PreprocY};
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assign intExp = zeroCntB - zeroCntA + 1;
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assign intSign = Signed & (SrcA[`XLEN - 1] ^ SrcB[`XLEN - 1]);
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