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Fixed an issue with direct map cache's nextway logic.

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Also found a small error in the replacement policy.
This commit is contained in:
Ross Thompson 2022-07-06 18:34:30 -05:00
parent cb33d2289b
commit bd46cf76a9
2 changed files with 4 additions and 3 deletions
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3
pipelined/src/cache/cache.sv vendored
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@ -185,7 +185,8 @@ module cache #(parameter LINELEN, NUMLINES, NUMWAYS, LOGWPL, WORDLEN, MUXINTER
flopenl #(NUMWAYS) FlushWayReg(.clk, .load(ResetOrFlushWay), .en(FlushWayCntEn),
.val({{NUMWAYS-1{1'b0}}, 1'b1}), .d(NextFlushWay), .q(FlushWay));
assign FlushWayFlag = FlushWay[NUMWAYS-1];
assign NextFlushWay = {FlushWay[NUMWAYS-2:0], FlushWay[NUMWAYS-1]};
if(NUMWAYS > 1) assign NextFlushWay = {FlushWay[NUMWAYS-2:0], FlushWay[NUMWAYS-1]};
else assign NextFlushWay = FlushWay[NUMWAYS-1];
/////////////////////////////////////////////////////////////////////////////////////////////
// Write Path: Write Enables

4
pipelined/src/cache/cachereplacementpolicy.sv vendored
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@ -59,8 +59,8 @@ module cachereplacementpolicy
// Replacement Bits: Register file
// Needs to be resettable for simulation, but could omit reset for synthesis ***
always_ff @(posedge clk)
if (reset) for (int set = 0; set < NUMLINES; set++) ReplacementBits[set] = '0;
else if (LRUWriteEnD) ReplacementBits[RAdrD] = NewReplacementD;
if (reset) for (int set = 0; set < NUMLINES; set++) ReplacementBits[set] <= '0;
else if (LRUWriteEnD) ReplacementBits[RAdrD] <= NewReplacementD;
assign LineReplacementBits = ReplacementBits[RAdrD];
genvar index;