Xavi/cvw
1
0
Fork 0
forked from Github_Repos/cvw
Code Issues Pull Requests Packages Projects Releases Wiki Activity

Merge branch 'bit-manip' of github.com:kipmacsaigoren/cvw into bit-manip

Browse Source
This commit is contained in:
Kip Macsai-Goren 2023-03-03 09:39:52 -08:00
commit 1e2c81ccca
8 changed files with 84 additions and 131 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
src/ieu/alu.sv
View File

@ -106,8 +106,8 @@ module alu #(parameter WIDTH=32) (
assign CondInvB = SubArith ? ~CondMaskB : CondMaskB;
assign {Carry, Sum} = CondShiftA + CondInvB + {{(WIDTH-1){1'b0}}, SubArith};
// Shifts
shifternew sh(.shA(shA), .rotA(rotA), .Amt(B[`LOG_XLEN-1:0]), .Right(Funct3[2]), .W64(W64), .Y(Shift), .Rotate(Rotate));
// Shifts (configurable for rotation)
shifter sh(.shA(shA), .rotA(rotA), .Amt(B[`LOG_XLEN-1:0]), .Right(Funct3[2]), .W64(W64), .Y(Shift), .Rotate(Rotate));
// Condition code flags are based on subtraction output Sum = A-B.
// Overflow occurs when the numbers being subtracted have the opposite sign

113
src/ieu/bmu/bmuctrl.sv
View File

@ -45,7 +45,8 @@ module bmuctrl(
input logic StallE, FlushE, // Stall, flush Execute stage
output logic [2:0] ALUSelectE,
output logic [3:0] BSelectE, // Indicates if ZBA_ZBB_ZBC_ZBS instruction in one-hot encoding
output logic [2:0] ZBBSelectE // ZBB mux select signal
output logic [2:0] ZBBSelectE, // ZBB mux select signal
output logic BRegWriteE // Indicates if it is a R type B instruction in Execute
);
logic [6:0] OpD; // Opcode in Decode stage
@ -69,85 +70,85 @@ module bmuctrl(
casez({OpD, Funct7D, Funct3D})
// ALUSelect_BSelect_ZBBSelect_BRegWrite_BW64_BALUOp
// ZBS
17'b0010011_0100100_001: BMUControlsD = `BMUCTRLW'b111_0001_000_101; // bclri
17'b0010011_0100100_001: BMUControlsD = `BMUCTRLW'b111_0001_000_1_0_1; // bclri
17'b0010011_0100101_001: if (`XLEN == 64)
BMUControlsD = `BMUCTRLW'b111_0001_000_101; // bclri (rv64)
BMUControlsD = `BMUCTRLW'b111_0001_000_1_0_1; // bclri (rv64)
else
BMUControlsD = `BMUCTRLW'b000_0000_000_000; // illegal instruction
17'b0010011_0100100_101: BMUControlsD = `BMUCTRLW'b101_0001_000_101; // bexti
BMUControlsD = `BMUCTRLW'b000_0000_000_0_0_0; // illegal instruction
17'b0010011_0100100_101: BMUControlsD = `BMUCTRLW'b101_0001_000_1_0_1; // bexti
17'b0010011_0100101_101: if (`XLEN == 64)
BMUControlsD = `BMUCTRLW'b101_0001_000_101; // bexti (rv64)
BMUControlsD = `BMUCTRLW'b101_0001_000_1_0_1; // bexti (rv64)
else
BMUControlsD = `BMUCTRLW'b000_0000_000_000; // illegal instruction
17'b0010011_0110100_001: BMUControlsD = `BMUCTRLW'b100_0001_000_101; // binvi
BMUControlsD = `BMUCTRLW'b000_0000_000_0_0_0; // illegal instruction
17'b0010011_0110100_001: BMUControlsD = `BMUCTRLW'b100_0001_000_1_0_1; // binvi
17'b0010011_0110101_001: if (`XLEN == 64)
BMUControlsD = `BMUCTRLW'b100_0001_000_101; // binvi (rv64)
BMUControlsD = `BMUCTRLW'b100_0001_000_1_0_1; // binvi (rv64)
else
BMUControlsD = `BMUCTRLW'b000_0000_000_000; // illegal instruction
17'b0010011_0010100_001: BMUControlsD = `BMUCTRLW'b110_0001_000_101; // bseti
BMUControlsD = `BMUCTRLW'b000_0000_000_0_0_0; // illegal instruction
17'b0010011_0010100_001: BMUControlsD = `BMUCTRLW'b110_0001_000_1_0_1; // bseti
17'b0010011_0010101_001: if (`XLEN == 64)
BMUControlsD = `BMUCTRLW'b110_0001_000_101; // bseti (rv64)
BMUControlsD = `BMUCTRLW'b110_0001_000_1_0_1; // bseti (rv64)
else
BMUControlsD = `BMUCTRLW'b000_0000_000_000; // illegal instruction
17'b0110011_0100100_001: BMUControlsD = `BMUCTRLW'b111_0001_000_101; // bclr
17'b0110011_0100100_101: BMUControlsD = `BMUCTRLW'b101_0001_000_101; // bext
17'b0110011_0110100_001: BMUControlsD = `BMUCTRLW'b100_0001_000_101; // binv
17'b0110011_0010100_001: BMUControlsD = `BMUCTRLW'b110_0001_000_101; // bset
17'b0?1?011_0?0000?_?01: BMUControlsD = `BMUCTRLW'b001_0000_000_101; // sra, srai, srl, srli, sll, slli
BMUControlsD = `BMUCTRLW'b000_0000_000_0_0_0; // illegal instruction
17'b0110011_0100100_001: BMUControlsD = `BMUCTRLW'b111_0001_000_1_0_1; // bclr
17'b0110011_0100100_101: BMUControlsD = `BMUCTRLW'b101_0001_000_1_0_1; // bext
17'b0110011_0110100_001: BMUControlsD = `BMUCTRLW'b100_0001_000_1_0_1; // binv
17'b0110011_0010100_001: BMUControlsD = `BMUCTRLW'b110_0001_000_1_0_1; // bset
17'b0?1?011_0?0000?_?01: BMUControlsD = `BMUCTRLW'b001_0000_000_1_0_1; // sra, srai, srl, srli, sll, slli
// ZBC
17'b0110011_0000101_0??: BMUControlsD = `BMUCTRLW'b000_0010_000_101; // ZBC instruction
17'b0110011_0000101_0??: BMUControlsD = `BMUCTRLW'b000_0010_000_1_0_1; // ZBC instruction
// ZBA
17'b0110011_0010000_010: BMUControlsD = `BMUCTRLW'b000_1000_000_101; // sh1add
17'b0110011_0010000_100: BMUControlsD = `BMUCTRLW'b000_1000_000_101; // sh2add
17'b0110011_0010000_110: BMUControlsD = `BMUCTRLW'b000_1000_000_101; // sh3add
17'b0111011_0010000_010: BMUControlsD = `BMUCTRLW'b000_1000_000_111; // sh1add.uw
17'b0111011_0010000_100: BMUControlsD = `BMUCTRLW'b000_1000_000_111; // sh2add.uw
17'b0111011_0010000_110: BMUControlsD = `BMUCTRLW'b000_1000_000_111; // sh3add.uw
17'b0111011_0000100_000: BMUControlsD = `BMUCTRLW'b000_1000_000_111; // add.uw
17'b0011011_000010?_001: BMUControlsD = `BMUCTRLW'b001_1000_000_111; // slli.uw
17'b0110011_0010000_010: BMUControlsD = `BMUCTRLW'b000_1000_000_1_0_1; // sh1add
17'b0110011_0010000_100: BMUControlsD = `BMUCTRLW'b000_1000_000_1_0_1; // sh2add
17'b0110011_0010000_110: BMUControlsD = `BMUCTRLW'b000_1000_000_1_0_1; // sh3add
17'b0111011_0010000_010: BMUControlsD = `BMUCTRLW'b000_1000_000_1_1_1; // sh1add.uw
17'b0111011_0010000_100: BMUControlsD = `BMUCTRLW'b000_1000_000_1_1_1; // sh2add.uw
17'b0111011_0010000_110: BMUControlsD = `BMUCTRLW'b000_1000_000_1_1_1; // sh3add.uw
17'b0111011_0000100_000: BMUControlsD = `BMUCTRLW'b000_1000_000_1_1_1; // add.uw
17'b0011011_000010?_001: BMUControlsD = `BMUCTRLW'b001_1000_000_1_1_1; // slli.uw
// ZBB
17'b0110011_0110000_001: BMUControlsD = `BMUCTRLW'b001_0100_111_101; // rol
17'b0111011_0110000_001: BMUControlsD = `BMUCTRLW'b001_0100_111_111; // rolw
17'b0110011_0110000_101: BMUControlsD = `BMUCTRLW'b001_0100_111_101; // ror
17'b0111011_0110000_101: BMUControlsD = `BMUCTRLW'b001_0100_111_111; // rorw
17'b0010011_0110000_101: BMUControlsD = `BMUCTRLW'b001_0100_111_101; // rori (rv32)
17'b0110011_0110000_001: BMUControlsD = `BMUCTRLW'b001_0100_111_1_0_1; // rol
17'b0111011_0110000_001: BMUControlsD = `BMUCTRLW'b001_0100_111_1_1_1; // rolw
17'b0110011_0110000_101: BMUControlsD = `BMUCTRLW'b001_0100_111_1_0_1; // ror
17'b0111011_0110000_101: BMUControlsD = `BMUCTRLW'b001_0100_111_1_1_1; // rorw
17'b0010011_0110000_101: BMUControlsD = `BMUCTRLW'b001_0100_111_1_0_1; // rori (rv32)
17'b0010011_0110001_101: if (`XLEN == 64)
BMUControlsD = `BMUCTRLW'b001_0100_111_101; // rori (rv64)
BMUControlsD = `BMUCTRLW'b001_0100_111_1_0_1; // rori (rv64)
else
BMUControlsD = `BMUCTRLW'b000_0000_000_000; // illegal instruction
BMUControlsD = `BMUCTRLW'b000_0000_000_0_0_0; // illegal instruction
17'b0011011_0110000_101: if (`XLEN == 64)
BMUControlsD = `BMUCTRLW'b001_0100_111_111; // roriw
BMUControlsD = `BMUCTRLW'b001_0100_111_1_1_1; // roriw
else
BMUControlsD = `BMUCTRLW'b000_0000_000_000; // illegal instruction
BMUControlsD = `BMUCTRLW'b000_0000_000_0_0_0; // illegal instruction
17'b0010011_0110000_001: if (Rs2D[2])
BMUControlsD = `BMUCTRLW'b000_0100_100_101; // sign extend instruction
BMUControlsD = `BMUCTRLW'b000_0100_100_1_0_1; // sign extend instruction
else
BMUControlsD = `BMUCTRLW'b000_0100_000_101; // count instruction
17'b0011011_0110000_001: BMUControlsD = `BMUCTRLW'b000_0100_000_111; // count word instruction
BMUControlsD = `BMUCTRLW'b000_0100_000_1_0_1; // count instruction
17'b0011011_0110000_001: BMUControlsD = `BMUCTRLW'b000_0100_000_1_1_1; // count word instruction
17'b0111011_0000100_100: if (`XLEN == 64)
BMUControlsD = `BMUCTRLW'b000_0100_100_101; // zexth (rv64)
BMUControlsD = `BMUCTRLW'b000_0100_100_1_0_1; // zexth (rv64)
else
BMUControlsD = `BMUCTRLW'b000_0000_000_000; // illegal instruction
BMUControlsD = `BMUCTRLW'b000_0000_000_0_0_0; // illegal instruction
17'b0110011_0000100_100: if (`XLEN == 32)
BMUControlsD = `BMUCTRLW'b000_0100_100_101; // zexth (rv32)
BMUControlsD = `BMUCTRLW'b000_0100_100_1_0_1; // zexth (rv32)
else
BMUControlsD = `BMUCTRLW'b000_0000_000_000; // illegal instruction
17'b0110011_0100000_111: BMUControlsD = `BMUCTRLW'b111_0100_111_101; // andn
17'b0110011_0100000_110: BMUControlsD = `BMUCTRLW'b110_0100_111_101; // orn
17'b0110011_0100000_100: BMUControlsD = `BMUCTRLW'b100_0100_111_101; // xnor
BMUControlsD = `BMUCTRLW'b000_0000_000_0_0_0; // illegal instruction
17'b0110011_0100000_111: BMUControlsD = `BMUCTRLW'b111_0100_111_1_0_1; // andn
17'b0110011_0100000_110: BMUControlsD = `BMUCTRLW'b110_0100_111_1_0_1; // orn
17'b0110011_0100000_100: BMUControlsD = `BMUCTRLW'b100_0100_111_1_0_1; // xnor
17'b0010011_0110101_101: if (`XLEN == 64)
BMUControlsD = `BMUCTRLW'b000_0100_011_101; // rev8 (rv64)
BMUControlsD = `BMUCTRLW'b000_0100_011_1_0_1; // rev8 (rv64)
else
BMUControlsD = `BMUCTRLW'b000_0000_000_000; // illegal instruction
BMUControlsD = `BMUCTRLW'b000_0000_000_0_0_0; // illegal instruction
17'b0010011_0110100_101: if (`XLEN == 32)
BMUControlsD = `BMUCTRLW'b000_0100_011_101; // rev8 (rv32)
BMUControlsD = `BMUCTRLW'b000_0100_011_1_0_1; // rev8 (rv32)
else
BMUControlsD = `BMUCTRLW'b000_0000_000_000; // illegal instruction
17'b0010011_0010100_101: BMUControlsD = `BMUCTRLW'b000_0100_011_101; // orc.b
17'b0110011_0000101_110: BMUControlsD = `BMUCTRLW'b000_0100_101_101; // max
17'b0110011_0000101_111: BMUControlsD = `BMUCTRLW'b000_0100_101_101; // maxu
17'b0110011_0000101_100: BMUControlsD = `BMUCTRLW'b000_0100_110_101; // min
17'b0110011_0000101_101: BMUControlsD = `BMUCTRLW'b000_0100_110_101; // minu
BMUControlsD = `BMUCTRLW'b000_0000_000_0_0_0; // illegal instruction
17'b0010011_0010100_101: BMUControlsD = `BMUCTRLW'b000_0100_011_1_0_1; // orc.b
17'b0110011_0000101_110: BMUControlsD = `BMUCTRLW'b000_0100_101_1_0_1; // max
17'b0110011_0000101_111: BMUControlsD = `BMUCTRLW'b000_0100_101_1_0_1; // maxu
17'b0110011_0000101_100: BMUControlsD = `BMUCTRLW'b000_0100_110_1_0_1; // min
17'b0110011_0000101_101: BMUControlsD = `BMUCTRLW'b000_0100_110_1_0_1; // minu
default: BMUControlsD = {Funct3D, {10'b0}}; // not B instruction or shift
endcase
@ -159,5 +160,5 @@ module bmuctrl(
// BMU Execute stage pipieline control register
flopenrc#(10) controlregBMU(clk, reset, FlushE, ~StallE, {ALUSelectD, BSelectD, ZBBSelectD}, {ALUSelectE, BSelectE, ZBBSelectE});
flopenrc#(11) controlregBMU(clk, reset, FlushE, ~StallE, {ALUSelectD, BSelectD, ZBBSelectD, BRegWriteD}, {ALUSelectE, BSelectE, ZBBSelectE, BRegWriteE});
endmodule

5
src/ieu/bmu/byte.sv
View File

@ -30,7 +30,8 @@
`include "wally-config.vh"
module byteUnit #(parameter WIDTH=32) (
input logic [WIDTH-1:0] A, B, // Operands
input logic [WIDTH-1:0] A, // Operands
input logic ByteSelect, // LSB of Immediate
output logic [WIDTH-1:0] ByteResult); // rev8, orcb result
logic [WIDTH-1:0] OrcBResult, Rev8Result;
@ -41,6 +42,6 @@ module byteUnit #(parameter WIDTH=32) (
assign Rev8Result[WIDTH-i-1:WIDTH-i-8] = A[i+7:i];
end
assign ByteResult = (B[0]) ? OrcBResult : Rev8Result;
assign ByteResult = (ByteSelect) ? OrcBResult : Rev8Result;
endmodule

2
src/ieu/bmu/zbb.sv
View File

@ -54,7 +54,7 @@ module zbb #(parameter WIDTH=32) (
logic [WIDTH-1:0] ExtResult; // sign/zero extend result
cnt #(WIDTH) cnt(.A(A), .B(B), .W64(W64), .CntResult(CntResult));
byteUnit #(WIDTH) bu(.A(A), .B(B), .ByteResult(ByteResult));
byteUnit #(WIDTH) bu(.A(A), .ByteSelect(B[0]), .ByteResult(ByteResult));
ext #(WIDTH) ext(.A(A), .B(B), .ExtResult(ExtResult));

12
src/ieu/bmu/zbc.sv
View File

@ -41,18 +41,18 @@ module zbc #(parameter WIDTH=32) (
bitreverse #(WIDTH) brA(.a(A), .b(RevA));
bitreverse #(WIDTH) brB(.a(B), .b(RevB));
//NOTE: Optimize this when doing decoder stuff.
// zbc input select mux
always_comb begin
casez (Funct3)
3'b001: begin //clmul
casez (Funct3[1:0])
2'b01: begin //clmul
x = A;
y = B;
end
3'b011: begin //clmulh
2'b11: begin //clmulh
x = {RevA[WIDTH-2:0], {1'b0}};
y = {{1'b0}, RevB[WIDTH-2:0]};
end
3'b010: begin //clmulr
2'b10: begin //clmulr
x = RevA;
y = RevB;
end
@ -66,7 +66,7 @@ module zbc #(parameter WIDTH=32) (
clmul #(WIDTH) clm(.A(x), .B(y), .ClmulResult(ClmulResult));
bitreverse #(WIDTH) brClmulResult(.a(ClmulResult), .b(RevClmulResult));
assign ZBCResult = (Funct3 == 3'b011 || Funct3 == 3'b010) ? RevClmulResult : ClmulResult;
assign ZBCResult = (Funct3[1]) ? RevClmulResult : ClmulResult;
endmodule

59
src/ieu/bmu/zbs.sv
View File

@ -1,59 +0,0 @@
///////////////////////////////////////////
// zbs.sv
//
// Written: Kevin Kim <kekim@hmc.edu> and Kip Macsai-Goren <kmacsaigoren@hmc.edu>
// Created: 31 January 2023
// Modified:
//
// Purpose: RISC-V single bit manipulation unit (ZBS instructions)
//
// Documentation: RISC-V System on Chip Design Chapter ***
//
// A component of the CORE-V-WALLY configurable RISC-V project.
//
// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
//
// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
//
// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
// except in compliance with the License, or, at your option, the Apache License version 2.0. You
// may obtain a copy of the License at
//
// https://solderpad.org/licenses/SHL-2.1/
//
// Unless required by applicable law or agreed to in writing, any work distributed under the
// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
// either express or implied. See the License for the specific language governing permissions
// and limitations under the License.
////////////////////////////////////////////////////////////////////////////////////////////////
`include "wally-config.vh"
module zbs #(parameter WIDTH=32) (
input logic [WIDTH-1:0] A, B, // Operands
//input logic [2:0] ALUControl, // With Funct3, indicates operation to perform
input logic [6:0] Funct7,
input logic [2:0] Funct3, // With ***Control, indicates operation to perform
output logic [WIDTH-1:0] ZBSResult); // ZBS result
logic [WIDTH-1:0] BMask, ClrResult, InvResult, ExtResult, SetResult;
decoder #($clog2(WIDTH)) maskgen (B[$clog2(WIDTH)-1:0], BMask);
assign InvResult = A ^ BMask;
assign ClrResult = A & ~BMask;
assign SetResult = A | BMask;
assign ExtResult = {{(WIDTH-1){1'b0}},{|(A & BMask)}};
always_comb begin
casez ({Funct7, Funct3})
10'b010010?_001: ZBSResult = ClrResult;
10'b010010?_101: ZBSResult = ExtResult;
10'b011010?_001: ZBSResult = InvResult;
10'b001010?_001: ZBSResult = SetResult;
default: ZBSResult = 0; // *** expand to include faults
endcase
end
endmodule

18
src/ieu/controller.sv
View File

@ -115,6 +115,7 @@ module controller(
logic unused;
logic BranchFlagE; // Branch flag to use (chosen between eq or lt)
logic IEURegWriteE; // Register write
logic BRegWriteE; // Register write from BMU controller in Execute Stage
logic IllegalERegAdrD; // RV32E attempts to write upper 16 registers
logic [1:0] AtomicE; // Atomic instruction
logic FenceD, FenceE; // Fence instruction
@ -241,17 +242,27 @@ module controller(
assign sltuD = (Funct3D == 3'b011);
assign subD = (Funct3D == 3'b000 & Funct7D[5] & OpD[5]); // OpD[5] needed to distinguish sub from addi
assign sraD = (Funct3D == 3'b101 & Funct7D[5]);
assign SubArithD = ALUOpD & (subD | sraD | sltD | sltuD | (`ZBS_SUPPORTED & (bextD | bclrD)) | (`ZBB_SUPPORTED & (andnD | ornD | xnorD))); // TRUE for R-type subtracts and sra, slt, sltu, and any B instruction that requires inverted operand
assign ALUControlD = {W64D, SubArithD, ALUOpD};
if (`ZBS_SUPPORTED | `ZBA_SUPPORTED | `ZBB_SUPPORTED | `ZBC_SUPPORTED) begin: bitmanipi //change the conditional expression to OR any Z supported flags
bmuctrl bmuctrl(.clk, .reset, .StallD, .FlushD, .InstrD, .ALUSelectD, .BSelectD, .ZBBSelectD, .BRegWriteD, BW64D, BALUOpD, .StallE, .FlushE, .ALUSelectE, .BSelectE, .ZBBSelectE);
bmuctrl bmuctrl(.clk, .reset, .StallD, .FlushD, .InstrD, .ALUSelectD, .BSelectD, .ZBBSelectD, .BRegWriteD, .BW64D, .BALUOpD, .StallE, .FlushE, .ALUSelectE, .BSelectE, .ZBBSelectE, .BRegWriteE);
assign RegWriteE = IEURegWriteE | FWriteIntE | BRegWriteE; // IRF register writes could come from IEU, BMU or FPU controllers
assign SubArithD = (ALUOpD | BALUOpD) & (subD | sraD | sltD | sltuD | (`ZBS_SUPPORTED & (bextD | bclrD)) | (`ZBB_SUPPORTED & (andnD | ornD | xnorD))); // TRUE for R-type subtracts and sra, slt, sltu, and any B instruction that requires inverted operand
assign ALUControlD = {(W64D | BW64D), SubArithD, ALUOpD};
end else begin: bitmanipi
assign ALUSelectD = Funct3D;
assign ALUSelectE = Funct3E;
assign BSelectE = 4'b0000;
assign BSelectD = 4'b0000;
assign ZBBSelectE = 3'b000;
assign BRegWriteD = 1'b0;
assign BW64D = 1'b0;
assign BALUOpD = 1'b0;
assign BRegWriteE = 1'b0;
assign RegWriteE = IEURegWriteE | FWriteIntE; // IRF register writes could come from IEU or FPU controllers
assign SubArithD = ALUOpD & (subD | sraD | sltD | sltuD);
assign ALUControlD = {W64D, SubArithD, ALUOpD};
end
// Fences
@ -288,7 +299,6 @@ module controller(
// Other execute stage controller signals
assign MemReadE = MemRWE[1];
assign SCE = (ResultSrcE == 3'b100);
assign RegWriteE = IEURegWriteE | FWriteIntE; // IRF register writes could come from IEU or FPU controllers
assign IntDivE = MDUE & Funct3E[2]; // Integer division operation
// Memory stage pipeline control register

2
src/ieu/shifter.sv
View File

@ -29,7 +29,7 @@
`include "wally-config.vh"
module shifternew (
module shifter (
input logic [`XLEN:0] shA, // shift Source
input logic [`XLEN-1:0] rotA, // rotate source
input logic [`LOG_XLEN-1:0] Amt, // Shift amount