forked from Github_Repos/cvw
fixed timeouts on GPIO test by enabling pins as inputs as well as outputs.
This commit is contained in:
Kip Macsai-Goren
parent
bd87af478a
commit
7630a0be42
@ -136,7 +136,7 @@ nowrap:
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time_loop:
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//wfi // *** this may now spin us forever in the loop???
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addi a3, a3, -1
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bnez a3, m_ext_loop // go through this loop for [a3 value] iterations before returning without performing interrupt
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bnez a3, time_loop // go through this loop for [a3 value] iterations before returning without performing interrupt
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ret
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cause_s_time_interrupt:
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@ -178,6 +178,7 @@ cause_m_ext_interrupt:
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li x28, 0x10060000 // load base GPIO memory location
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li x29, 0x1
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sw x29, 0x08(x28) // enable the first pin as an output
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sw x29, 0x04(x28) // enable the first pin as an input as well to cause the interrupt to fire
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sw x0, 0x1C(x28) // clear rise_ip
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sw x0, 0x24(x28) // clear fall_ip
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@ -214,6 +215,7 @@ cause_s_ext_interrupt_GPIO:
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li x28, 0x10060000 // load base GPIO memory location
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li x29, 0x1
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sw x29, 0x08(x28) // enable the first pin as an output
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sw x29, 0x04(x28) // enable the first pin as an input as well to cause the interrupt to fire
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sw x0, 0x1C(x28) // clear rise_ip
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sw x0, 0x24(x28) // clear fall_ip
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@ -225,7 +227,7 @@ cause_s_ext_interrupt_GPIO:
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s_ext_loop:
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//wfi
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addi a3, a3, -1
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bnez a3, m_ext_loop // go through this loop for [a3 value] iterations before returning without performing interrupt
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bnez a3, s_ext_loop // go through this loop for [a3 value] iterations before returning without performing interrupt
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ret
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end_trap_triggers:
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@ -72,7 +72,7 @@ j end_trap_triggers
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cause_instr_addr_misaligned:
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// cause a misaligned address trap
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auipc x28, 0 // get current PC, which is aligned
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addi x28, x28, 0x3 // add 1 to pc to create misaligned address
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addi x28, x28, 0x2 // add 2 to pc to create misaligned address (Assumes compressed instructions are disabled)
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jr x28 // cause instruction address midaligned trap
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ret
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@ -138,7 +138,7 @@ nowrap:
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time_loop:
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//wfi // *** this may now spin us forever in the loop???
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addi a3, a3, -1
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bnez a3, m_ext_loop // go through this loop for [a3 value] iterations before returning without performing interrupt
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bnez a3, time_loop // go through this loop for [a3 value] iterations before returning without performing interrupt
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ret
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cause_s_time_interrupt:
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@ -180,6 +180,7 @@ cause_m_ext_interrupt:
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li x28, 0x10060000 // load base GPIO memory location
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li x29, 0x1
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sw x29, 0x08(x28) // enable the first pin as an output
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sw x29, 0x04(x28) // enable the first pin as an input as well to cause the interrupt to fire
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sw x0, 0x1C(x28) // clear rise_ip
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sw x0, 0x24(x28) // clear fall_ip
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@ -216,6 +217,7 @@ cause_s_ext_interrupt_GPIO:
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li x28, 0x10060000 // load base GPIO memory location
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li x29, 0x1
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sw x29, 0x08(x28) // enable the first pin as an output
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sw x29, 0x04(x28) // enable the first pin as an input as well to cause the interrupt to fire
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sw x0, 0x1C(x28) // clear rise_ip
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sw x0, 0x24(x28) // clear fall_ip
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@ -227,7 +229,7 @@ cause_s_ext_interrupt_GPIO:
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s_ext_loop:
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//wfi
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addi a3, a3, -1
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bnez a3, m_ext_loop // go through this loop for [a3 value] iterations before returning without performing interrupt
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bnez a3, s_ext_loop // go through this loop for [a3 value] iterations before returning without performing interrupt
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ret
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end_trap_triggers:
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@ -354,7 +356,7 @@ trap_stack_saved_\MODE\(): // jump here after handling vectored interupt since w
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csrr x1, \MODE\()cause
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li x5, 0x8000000000000000 // if msb is set, it is an interrupt
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and x5, x5, x1
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bnez x5, interrupt_handler_\MODE\() // return from interrupt
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bnez x5, interrupt_handler_\MODE\()
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// Other trap handling is specified in the vector Table
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la x5, exception_vector_table_\MODE\()
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slli x1, x1, 3 // multiply cause by 8 to get offset in vector Table
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@ -370,7 +372,7 @@ interrupt_handler_\MODE\():
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jr x5 // and jump to the handler
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segfault_\MODE\():
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sd x7, -24(sp) // restore registers from stack before faulting
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ld x7, -24(sp) // restore registers from stack before faulting
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ld x5, -16(sp)
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ld x1, -8(sp)
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j terminate_test // halt program.
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@ -426,6 +428,8 @@ trapreturn_finished_\MODE\():
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csrrw sp, \MODE\()scratch, sp // switch sp and scratch stack back to restore the non-trap stack pointer
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\MODE\()ret // return from trap
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// specific exception handlers
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ecallhandler_\MODE\():
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// Check input parameter a0. encoding above.
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li x5, 2 // case 2: change to machine mode
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@ -442,7 +446,7 @@ ecallhandler_changetomachinemode_\MODE\():
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// note that it is impossible to return to M mode after a trap delegated to S mode
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li x1, 0b1100000000000
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csrs \MODE\()status, x1
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j trapreturn_\MODE\()
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j trapreturn_\MODE\()
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ecallhandler_changetosupervisormode_\MODE\():
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// Force status.MPP (bits 12:11) and status.SPP (bit 8) to 01 to enter supervisor mode after (m/s)ret
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@ -478,6 +482,9 @@ addr_misaligned_\MODE\():
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breakpt_\MODE\():
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j trapreturn_\MODE\()
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// Vectored interrupt handlers: record the fact that the handler went to the correct vector and then continue to handling
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// note: does not mess up any registers, saves and restores them to the stack instead.
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s_soft_vector_\MODE\():
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csrrw sp, \MODE\()scratch, sp // swap sp and scratch so we can use the scratch stack in the trap hanler without messing up sp's value or the stack itself.
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sd x5, -8(sp) // put x5 on the scratch stack before messing with it
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@ -521,6 +528,8 @@ vectored_int_end_\MODE\():
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ld x5, -8(sp) // restore x5 before continuing to handle trap in case its needed.
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j trap_stack_saved_\MODE\()
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// specific interrupt handlers
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soft_interrupt_\MODE\():
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la x5, 0x02000000 // Reset by clearing MSIP interrupt from CLINT
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sw x0, 0(x5)
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@ -575,8 +584,6 @@ ext_interrupt_\MODE\():
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j trapreturn_finished_\MODE\() // return to the code at ra value from before trap
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// Table of trap behavior
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// lists what to do on each exception (not interrupts)
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// unexpected exceptions should cause segfaults for easy detection
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@ -1023,8 +1030,6 @@ goto_sv39:
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or x7, x7, x29 // put ASID into the correct field of SATP
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or x7, x7, x28 // Base Pagetable physical page number, satp.PPN field.
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csrw satp, x7
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li x29, 0xFFFFFFFFFFFFF888
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sfence.vma x0, x29 // just an attempt ***
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j test_loop // go to next test case
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goto_sv48:
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