forked from Github_Repos/cvw
Removed TrapM from the LSU and IFU. TrapM is replaced with FlushW for both. (Don't like this for the IFU).
FlushW prevents writting the cache, dtim, and bus state. FlushW still gates HTRANS. FlushW does not impact the mealy outputs of the cache and bus FSMs and hazard is updated to not stall W if we get a trap.
This commit is contained in:
Ross Thompson
parent
922513c22f
commit
42c0a10d07
7
pipelined/src/cache/cache.sv
vendored
7
pipelined/src/cache/cache.sv
vendored
@ -34,6 +34,7 @@ module cache #(parameter LINELEN, NUMLINES, NUMWAYS, LOGBWPL, WORDLEN, MUXINTE
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input logic clk,
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input logic reset,
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// cpu side
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input logic Flush,
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input logic CPUBusy,
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input logic [1:0] CacheRW,
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input logic [1:0] CacheAtomic,
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@ -125,11 +126,11 @@ module cache #(parameter LINELEN, NUMLINES, NUMWAYS, LOGBWPL, WORDLEN, MUXINTE
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cacheway #(NUMLINES, LINELEN, TAGLEN, OFFSETLEN, SETLEN)
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CacheWays[NUMWAYS-1:0](.clk, .reset, .ce(SRAMEnable), .RAdr, .PAdr, .CacheWriteData, .LineByteMask,
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.SetValidWay, .ClearValidWay, .SetDirtyWay, .ClearDirtyWay, .SelEvict, .VictimWay,
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.FlushWay, .SelFlush, .ReadDataLineWay, .HitWay, .VictimDirtyWay, .VictimTagWay,
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.FlushWay, .SelFlush, .ReadDataLineWay, .HitWay, .VictimDirtyWay, .VictimTagWay, .Flush,
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.Invalidate(InvalidateCache));
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if(NUMWAYS > 1) begin:vict
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cachereplacementpolicy #(NUMWAYS, SETLEN, OFFSETLEN, NUMLINES) cachereplacementpolicy(
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.clk, .reset, .ce(SRAMEnable), .HitWay, .VictimWay, .RAdr, .LRUWriteEn);
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.clk, .reset, .ce(SRAMEnable), .HitWay, .VictimWay, .RAdr, .LRUWriteEn(LRUWriteEn & ~Flush));
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end else assign VictimWay = 1'b1; // one hot.
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assign CacheHit = | HitWay;
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assign VictimDirty = | VictimDirtyWay;
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@ -206,7 +207,7 @@ module cache #(parameter LINELEN, NUMLINES, NUMWAYS, LOGBWPL, WORDLEN, MUXINTE
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// Cache FSM
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/////////////////////////////////////////////////////////////////////////////////////////////
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cachefsm cachefsm(.clk, .reset, .CacheBusRW, .CacheBusAck,
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.CacheRW, .CacheAtomic, .CPUBusy,
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.Flush, .CacheRW, .CacheAtomic, .CPUBusy,
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.CacheHit, .VictimDirty, .CacheStall, .CacheCommitted,
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.CacheMiss, .CacheAccess, .SelAdr,
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.ClearValid, .ClearDirty, .SetDirty,
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42
pipelined/src/cache/cachefsm.sv
vendored
42
pipelined/src/cache/cachefsm.sv
vendored
@ -34,6 +34,7 @@ module cachefsm
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(input logic clk,
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input logic reset,
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// inputs from IEU
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input logic Flush,
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input logic [1:0] CacheRW,
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input logic [1:0] CacheAtomic,
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input logic FlushCache,
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@ -75,9 +76,8 @@ module cachefsm
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logic resetDelay;
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logic AMO;
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logic DoAMO, DoRead, DoWrite, DoFlush;
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logic DoAnyUpdateHit, DoAnyHit;
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logic DoAnyMiss;
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logic AnyUpdateHit, AnyHit;
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logic AnyMiss;
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logic FlushFlag, FlushWayAndNotAdrFlag;
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typedef enum logic [3:0] {STATE_READY, // hit states
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@ -94,19 +94,15 @@ module cachefsm
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(* mark_debug = "true" *) statetype CurrState, NextState;
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assign DoFlush = FlushCache;
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assign AMO = CacheAtomic[1] & (&CacheRW);
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assign DoAMO = AMO;
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assign DoRead = CacheRW[1];
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assign DoWrite = CacheRW[0];
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assign DoAnyMiss = (DoAMO | DoRead | DoWrite) & ~CacheHit & ~InvalidateCache;
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assign DoAnyUpdateHit = (DoAMO | DoWrite) & CacheHit;
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assign DoAnyHit = DoAnyUpdateHit | (DoRead & CacheHit);
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assign AnyMiss = (AMO | CacheRW[1] | CacheRW[0]) & ~CacheHit & ~InvalidateCache;
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assign AnyUpdateHit = (AMO | CacheRW[0]) & CacheHit;
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assign AnyHit = AnyUpdateHit | (CacheRW[1] & CacheHit);
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assign FlushFlag = FlushAdrFlag & FlushWayFlag;
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// outputs for the performance counters.
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assign CacheAccess = (DoAMO | DoRead | DoWrite) & CurrState == STATE_READY;
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assign CacheAccess = (AMO | CacheRW[1] | CacheRW[0]) & CurrState == STATE_READY;
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assign CacheMiss = CacheAccess & ~CacheHit;
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// special case on reset. When the fsm first exists reset the
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@ -115,18 +111,18 @@ module cachefsm
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flop #(1) resetDelayReg(.clk, .d(reset), .q(resetDelay));
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always_ff @(posedge clk)
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if (reset) CurrState <= #1 STATE_READY;
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if (reset | Flush) CurrState <= #1 STATE_READY;
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else CurrState <= #1 NextState;
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always_comb begin
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NextState = STATE_READY;
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case (CurrState)
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STATE_READY: if(InvalidateCache) NextState = STATE_READY;
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else if(DoFlush) NextState = STATE_FLUSH;
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else if(FlushCache) NextState = STATE_FLUSH;
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// Delayed LRU update. Cannot check if victim line is dirty on this cycle.
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// To optimize do the fetch first, then eviction if necessary.
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else if(DoAnyMiss & ~VictimDirty) NextState = STATE_MISS_FETCH_WDV;
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else if(DoAnyMiss & VictimDirty) NextState = STATE_MISS_EVICT_DIRTY;
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else if(AnyMiss & ~VictimDirty) NextState = STATE_MISS_FETCH_WDV;
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else if(AnyMiss & VictimDirty) NextState = STATE_MISS_EVICT_DIRTY;
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else NextState = STATE_READY;
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STATE_MISS_FETCH_WDV: if(CacheBusAck) NextState = STATE_MISS_WRITE_CACHE_LINE;
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else NextState = STATE_MISS_FETCH_WDV;
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@ -155,7 +151,7 @@ module cachefsm
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// com back to CPU
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assign CacheCommitted = CurrState != STATE_READY;
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assign CacheStall = (CurrState == STATE_READY & (DoFlush | DoAnyMiss)) |
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assign CacheStall = (CurrState == STATE_READY & (FlushCache | AnyMiss)) |
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(CurrState == STATE_MISS_FETCH_WDV) |
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(CurrState == STATE_MISS_EVICT_DIRTY) |
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(CurrState == STATE_MISS_WRITE_CACHE_LINE & ~(AMO | CacheRW[0])) | // this cycle writes the sram, must keep stalling so the next cycle can read the next hit/miss unless its a write.
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@ -165,16 +161,16 @@ module cachefsm
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(CurrState == STATE_FLUSH_WRITE_BACK & ~(FlushFlag) & CacheBusAck);
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// write enables internal to cache
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assign SetValid = CurrState == STATE_MISS_WRITE_CACHE_LINE;
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assign SetDirty = (CurrState == STATE_READY & DoAnyUpdateHit) |
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assign SetDirty = (CurrState == STATE_READY & AnyUpdateHit) |
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(CurrState == STATE_MISS_WRITE_CACHE_LINE & (AMO | CacheRW[0]));
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assign ClearValid = '0;
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assign ClearDirty = (CurrState == STATE_MISS_WRITE_CACHE_LINE & ~(AMO | CacheRW[0])) |
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(CurrState == STATE_FLUSH_WRITE_BACK & CacheBusAck);
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assign LRUWriteEn = (CurrState == STATE_READY & DoAnyHit) |
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assign LRUWriteEn = (CurrState == STATE_READY & AnyHit) |
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(CurrState == STATE_MISS_WRITE_CACHE_LINE);
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// Flush and eviction controls
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assign SelEvict = (CurrState == STATE_MISS_EVICT_DIRTY & ~CacheBusAck) |
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(CurrState == STATE_READY & DoAnyMiss & VictimDirty);
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(CurrState == STATE_READY & AnyMiss & VictimDirty);
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assign SelFlush = (CurrState == STATE_FLUSH) | (CurrState == STATE_FLUSH_CHECK) |
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(CurrState == STATE_FLUSH_INCR) | (CurrState == STATE_FLUSH_WRITE_BACK);
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assign FlushWayAndNotAdrFlag = FlushWayFlag & ~FlushAdrFlag;
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@ -185,11 +181,11 @@ module cachefsm
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assign FlushAdrCntRst = (CurrState == STATE_READY);
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assign FlushWayCntRst = (CurrState == STATE_READY) | (CurrState == STATE_FLUSH_INCR);
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// Bus interface controls
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assign CacheBusRW[1] = (CurrState == STATE_READY & DoAnyMiss & ~VictimDirty) |
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assign CacheBusRW[1] = (CurrState == STATE_READY & AnyMiss & ~VictimDirty) |
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(CurrState == STATE_MISS_FETCH_WDV & ~CacheBusAck) |
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(CurrState == STATE_MISS_EVICT_DIRTY & CacheBusAck);
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// assign CacheBusRW[1] = CurrState == STATE_READY & DoAnyMiss;
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assign CacheBusRW[0] = (CurrState == STATE_READY & DoAnyMiss & VictimDirty) |
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// assign CacheBusRW[1] = CurrState == STATE_READY & AnyMiss;
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assign CacheBusRW[0] = (CurrState == STATE_READY & AnyMiss & VictimDirty) |
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(CurrState == STATE_MISS_EVICT_DIRTY & ~CacheBusAck) |
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(CurrState == STATE_FLUSH_WRITE_BACK & ~CacheBusAck) |
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(CurrState == STATE_FLUSH_CHECK & VictimDirty);
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@ -197,7 +193,7 @@ module cachefsm
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// (CurrState == STATE_FLUSH_CHECK & VictimDirty);
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// **** can this be simplified?
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assign SelAdr = (CurrState == STATE_READY & ((AMO | CacheRW[0]) & CacheHit)) | // changes if store delay hazard removed
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(CurrState == STATE_READY & (DoAnyMiss)) |
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(CurrState == STATE_READY & (AnyMiss)) |
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(CurrState == STATE_MISS_FETCH_WDV) |
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(CurrState == STATE_MISS_EVICT_DIRTY) |
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(CurrState == STATE_MISS_WRITE_CACHE_LINE) |
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13
pipelined/src/cache/cacheway.sv
vendored
13
pipelined/src/cache/cacheway.sv
vendored
@ -48,6 +48,7 @@ module cacheway #(parameter NUMLINES=512, parameter LINELEN = 256, TAGLEN = 26,
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input logic VictimWay,
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input logic FlushWay,
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input logic Invalidate,
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input logic Flush,
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// input logic [(`XLEN-1)/8:0] ByteMask,
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input logic [LINELEN/8-1:0] LineByteMask,
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@ -86,7 +87,7 @@ module cacheway #(parameter NUMLINES=512, parameter LINELEN = 256, TAGLEN = 26,
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sram1p1rw #(.DEPTH(NUMLINES), .WIDTH(TAGLEN)) CacheTagMem(.clk, .ce,
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.addr(RAdr), .dout(ReadTag), .bwe('1),
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.din(PAdr[`PA_BITS-1:OFFSETLEN+INDEXLEN]), .we(SetValidWay));
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.din(PAdr[`PA_BITS-1:OFFSETLEN+INDEXLEN]), .we(SetValidWay & ~Flush));
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// AND portion of distributed tag multiplexer
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mux2 #(1) seltagmux(VictimWay, FlushWay, SelFlush, SelTag);
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@ -109,7 +110,7 @@ module cacheway #(parameter NUMLINES=512, parameter LINELEN = 256, TAGLEN = 26,
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sram1p1rw #(.DEPTH(NUMLINES), .WIDTH(SRAMLEN)) CacheDataMem(.clk, .ce, .addr(RAdr),
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.dout(ReadDataLine[SRAMLEN*(words+1)-1:SRAMLEN*words]),
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.din(CacheWriteData[SRAMLEN*(words+1)-1:SRAMLEN*words]),
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.we(SelectedWriteWordEn), .bwe(FinalByteMask[SRAMLENINBYTES*(words+1)-1:SRAMLENINBYTES*words]));
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.we(SelectedWriteWordEn & ~Flush), .bwe(FinalByteMask[SRAMLENINBYTES*(words+1)-1:SRAMLENINBYTES*words]));
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end
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// AND portion of distributed read multiplexers
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@ -123,8 +124,8 @@ module cacheway #(parameter NUMLINES=512, parameter LINELEN = 256, TAGLEN = 26,
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always_ff @(posedge clk) begin // Valid bit array,
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if (reset | Invalidate) ValidBits <= #1 '0;
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if(ce) begin Valid <= #1 ValidBits[RAdr];
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if (SetValidWay) ValidBits[RAdr] <= #1 1'b1;
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else if (ClearValidWay) ValidBits[RAdr] <= #1 1'b0;
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if (SetValidWay & ~Flush) ValidBits[RAdr] <= #1 1'b1;
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else if (ClearValidWay & ~Flush) ValidBits[RAdr] <= #1 1'b0;
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end
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end
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@ -138,8 +139,8 @@ module cacheway #(parameter NUMLINES=512, parameter LINELEN = 256, TAGLEN = 26,
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if (reset) DirtyBits <= #1 {NUMLINES{1'b0}};
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if(ce) begin
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Dirty <= #1 DirtyBits[RAdr];
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if (SetDirtyWay) DirtyBits[RAdr] <= #1 1'b1;
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else if (ClearDirtyWay) DirtyBits[RAdr] <= #1 1'b0;
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if (SetDirtyWay & ~Flush) DirtyBits[RAdr] <= #1 1'b1;
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else if (ClearDirtyWay & ~Flush) DirtyBits[RAdr] <= #1 1'b0;
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end
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end
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end else assign Dirty = 1'b0;
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@ -56,6 +56,7 @@ module ahbcacheinterface #(parameter WORDSPERLINE, LINELEN, LOGWPL, CACHE_ENABLE
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input logic Cacheable,
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// lsu/ifu interface
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input logic Flush,
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input logic [`PA_BITS-1:0] PAdr,
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input logic [1:0] BusRW,
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input logic CPUBusy,
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@ -83,7 +84,7 @@ module ahbcacheinterface #(parameter WORDSPERLINE, LINELEN, LOGWPL, CACHE_ENABLE
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mux2 #(3) sizemux(.d0(Funct3), .d1(`XLEN == 32 ? 3'b010 : 3'b011), .s(Cacheable), .y(HSIZE));
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buscachefsm #(WordCountThreshold, LOGWPL, CACHE_ENABLED) AHBBuscachefsm(
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.HCLK, .HRESETn, .BusRW, .CPUBusy, .BusCommitted, .BusStall, .CaptureEn, .SelBusWord,
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.HCLK, .HRESETn, .Flush, .BusRW, .CPUBusy, .BusCommitted, .BusStall, .CaptureEn, .SelBusWord,
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.CacheBusRW, .CacheBusAck, .WordCount, .WordCountDelayed,
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.HREADY, .HTRANS, .HWRITE, .HBURST);
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endmodule
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@ -47,6 +47,7 @@ module ahbinterface #(parameter LSU = 0) // **** modify to use LSU/ifu parameter
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output logic [`XLEN/8-1:0] HWSTRB,
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// lsu/ifu interface
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input logic Flush,
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input logic [1:0] BusRW,
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input logic [`XLEN/8-1:0] ByteMask,
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input logic [`XLEN-1:0] WriteData,
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@ -71,7 +72,7 @@ module ahbinterface #(parameter LSU = 0) // **** modify to use LSU/ifu parameter
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assign HWSTRB = '0;
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end
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busfsm busfsm(.HCLK, .HRESETn, .BusRW,
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busfsm busfsm(.HCLK, .HRESETn, .Flush, .BusRW,
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.BusCommitted, .CPUBusy, .BusStall, .CaptureEn, .HREADY,
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.HTRANS, .HWRITE);
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endmodule
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@ -38,6 +38,7 @@ module buscachefsm #(parameter integer WordCountThreshold,
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input logic HRESETn,
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// IEU interface
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input logic Flush,
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input logic [1:0] BusRW,
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input logic CPUBusy,
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output logic BusCommitted,
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@ -77,7 +78,7 @@ module buscachefsm #(parameter integer WordCountThreshold,
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logic CacheAccess;
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always_ff @(posedge HCLK)
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if (~HRESETn) CurrState <= #1 ADR_PHASE;
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if (~HRESETn | Flush) CurrState <= #1 ADR_PHASE;
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else CurrState <= #1 NextState;
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always_comb begin
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@ -135,7 +136,7 @@ module buscachefsm #(parameter integer WordCountThreshold,
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assign BusCommitted = CurrState != ADR_PHASE;
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// AHB bus interface
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assign HTRANS = (CurrState == ADR_PHASE & HREADY & (|BusRW | |CacheBusRW)) |
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assign HTRANS = (CurrState == ADR_PHASE & HREADY & (|BusRW | |CacheBusRW) & ~Flush) |
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(CacheAccess & FinalWordCount & |CacheBusRW & HREADY) ? AHB_NONSEQ : // if we have a pipelined request
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(CacheAccess & |WordCount) ? (`BURST_EN ? AHB_SEQ : AHB_NONSEQ) : AHB_IDLE;
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@ -36,6 +36,7 @@ module busfsm
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input logic HRESETn,
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// IEU interface
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input logic Flush,
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input logic [1:0] BusRW,
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input logic CPUBusy,
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output logic BusCommitted,
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@ -55,8 +56,8 @@ module busfsm
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(* mark_debug = "true" *) busstatetype CurrState, NextState;
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always_ff @(posedge HCLK)
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if (~HRESETn) CurrState <= #1 ADR_PHASE;
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else CurrState <= #1 NextState;
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if (~HRESETn | Flush) CurrState <= #1 ADR_PHASE;
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else CurrState <= #1 NextState;
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always_comb begin
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case(CurrState)
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@ -76,7 +77,7 @@ module busfsm
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assign BusCommitted = CurrState != ADR_PHASE;
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assign HTRANS = (CurrState == ADR_PHASE & HREADY & |BusRW) ? AHB_NONSEQ : AHB_IDLE;
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assign HTRANS = (CurrState == ADR_PHASE & HREADY & |BusRW & ~Flush) ? AHB_NONSEQ : AHB_IDLE;
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assign HWRITE = BusRW[0];
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assign CaptureEn = CurrState == DATA_PHASE;
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@ -70,7 +70,7 @@ module hazard(
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// WFI terminates if any enabled interrupt is pending, even if global interrupts are disabled. It could also terminate with TW trap
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// assign StallMCause = (wfiM & (~TrapM & ~IntPendingM)); // | FDivBusyE;
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assign StallMCause = ((wfiM) & (~TrapM & ~IntPendingM)); //*** Ross: should FDivBusyE trigger StallECause rather than StallMCause similar to DivBusyE?
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assign StallWCause = LSUStallM | IFUStallF | (FDivBusyE & ~TrapM & ~IntPendingM);
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assign StallWCause = ((IFUStallF | LSUStallM) & ~TrapM) | (FDivBusyE & ~TrapM & ~IntPendingM);
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assign #1 StallF = StallFCause | StallD;
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assign #1 StallD = StallDCause | StallE;
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@ -34,7 +34,7 @@
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module ifu (
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input logic clk, reset,
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input logic StallF, StallD, StallE, StallM,
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input logic FlushF, FlushD, FlushE, FlushM,
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input logic FlushF, FlushD, FlushE, FlushM, FlushW,
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// Bus interface
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(* mark_debug = "true" *) input logic [`XLEN-1:0] HRDATA,
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(* mark_debug = "true" *) output logic [`PA_BITS-1:0] IFUHADDR,
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@ -130,7 +130,7 @@ module ifu (
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if(`C_SUPPORTED) begin : SpillSupport
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spillsupport #(`ICACHE) spillsupport(.clk, .reset, .StallF, .PCF, .PCPlusUpperF, .PCNextF, .InstrRawF(InstrRawF),
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spillsupport #(`ICACHE) spillsupport(.clk, .reset, .StallF, .Flush(TrapM), .PCF, .PCPlusUpperF, .PCNextF, .InstrRawF(InstrRawF),
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.InstrDAPageFaultF, .IFUCacheBusStallF, .ITLBMissF, .PCNextFSpill, .PCFSpill,
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.SelNextSpillF, .PostSpillInstrRawF, .CompressedF);
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end else begin : NoSpillSupport
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@ -194,7 +194,7 @@ module ifu (
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assign CommittedF = CacheCommittedF | BusCommittedF;
|
||||
|
||||
logic IgnoreRequest;
|
||||
assign IgnoreRequest = ITLBMissF | TrapM;
|
||||
assign IgnoreRequest = ITLBMissF | FlushD;
|
||||
|
||||
// The IROM uses untranslated addresses, so it is not compatible with virtual memory.
|
||||
if (`IROM_SUPPORTED) begin : irom
|
||||
@ -215,12 +215,12 @@ module ifu (
|
||||
logic [1:0] CacheBusRW, BusRW, CacheRWF;
|
||||
|
||||
//assign BusRW = IFURWF & ~{IgnoreRequest, IgnoreRequest} & ~{CacheableF, CacheableF} & ~{SelIROM, SelIROM};
|
||||
assign BusRW = ~IgnoreRequest & ~CacheableF & ~SelIROM ? IFURWF : '0;
|
||||
assign CacheRWF = ~IgnoreRequest & CacheableF & ~SelIROM ? IFURWF : '0;
|
||||
assign BusRW = ~ITLBMissF & ~CacheableF & ~SelIROM ? IFURWF : '0;
|
||||
assign CacheRWF = ~ITLBMissF & CacheableF & ~SelIROM ? IFURWF : '0;
|
||||
cache #(.LINELEN(`ICACHE_LINELENINBITS),
|
||||
.NUMLINES(`ICACHE_WAYSIZEINBYTES*8/`ICACHE_LINELENINBITS),
|
||||
.NUMWAYS(`ICACHE_NUMWAYS), .LOGBWPL(LOGBWPL), .WORDLEN(32), .MUXINTERVAL(16), .DCACHE(0))
|
||||
icache(.clk, .reset, .CPUBusy,
|
||||
icache(.clk, .reset, .Flush(FlushW), .CPUBusy,
|
||||
.FetchBuffer, .CacheBusAck(ICacheBusAck),
|
||||
.CacheBusAdr(ICacheBusAdr), .CacheStall(ICacheStallF),
|
||||
.CacheBusRW,
|
||||
@ -237,7 +237,7 @@ module ifu (
|
||||
ahbcacheinterface #(WORDSPERLINE, LINELEN, LOGBWPL, `ICACHE)
|
||||
ahbcacheinterface(.HCLK(clk), .HRESETn(~reset),
|
||||
.HRDATA,
|
||||
.CacheBusRW, .HSIZE(IFUHSIZE), .HBURST(IFUHBURST), .HTRANS(IFUHTRANS),
|
||||
.Flush(FlushW), .CacheBusRW, .HSIZE(IFUHSIZE), .HBURST(IFUHBURST), .HTRANS(IFUHTRANS),
|
||||
.Funct3(3'b010), .HADDR(IFUHADDR), .HREADY(IFUHREADY), .HWRITE(IFUHWRITE), .CacheBusAdr(ICacheBusAdr),
|
||||
.WordCount(), .Cacheable(CacheableF), .SelBusWord(),
|
||||
.CacheBusAck(ICacheBusAck),
|
||||
@ -252,11 +252,11 @@ module ifu (
|
||||
logic CaptureEn;
|
||||
logic [31:0] FetchBuffer;
|
||||
logic [1:0] BusRW;
|
||||
assign BusRW = ~IgnoreRequest & ~SelIROM ? IFURWF : '0;
|
||||
assign BusRW = ~ITLBMissF & ~SelIROM ? IFURWF : '0;
|
||||
// assign BusRW = IFURWF & ~{IgnoreRequest, IgnoreRequest} & ~{SelIROM, SelIROM};
|
||||
assign IFUHSIZE = 3'b010;
|
||||
|
||||
ahbinterface #(0) ahbinterface(.HCLK(clk), .HRESETn(~reset), .HREADY(IFUHREADY),
|
||||
ahbinterface #(0) ahbinterface(.HCLK(clk), .Flush(FlushW), .HRESETn(~reset), .HREADY(IFUHREADY),
|
||||
.HRDATA(HRDATA), .HTRANS(IFUHTRANS), .HWRITE(IFUHWRITE), .HWDATA(),
|
||||
.HWSTRB(), .BusRW, .ByteMask(), .WriteData('0),
|
||||
.CPUBusy, .BusStall, .BusCommitted(BusCommittedF), .FetchBuffer(FetchBuffer));
|
||||
|
||||
@ -35,7 +35,7 @@
|
||||
module spillsupport #(parameter CACHE_ENABLED)
|
||||
(input logic clk,
|
||||
input logic reset,
|
||||
input logic StallF,
|
||||
input logic StallF, Flush,
|
||||
input logic [`XLEN-1:0] PCF,
|
||||
input logic [`XLEN-3:0] PCPlusUpperF,
|
||||
input logic [`XLEN-1:0] PCNextF,
|
||||
@ -61,7 +61,7 @@ module spillsupport #(parameter CACHE_ENABLED)
|
||||
|
||||
mux2 #(`XLEN) pcplus2mux(.d0({PCF[`XLEN-1:2], 2'b10}), .d1({PCPlusUpperF, 2'b00}),
|
||||
.s(PCF[1]), .y(PCPlus2F));
|
||||
mux2 #(`XLEN) pcnextspillmux(.d0(PCNextF), .d1(PCPlus2F), .s(SelNextSpillF),
|
||||
mux2 #(`XLEN) pcnextspillmux(.d0(PCNextF), .d1(PCPlus2F), .s(SelNextSpillF & ~Flush),
|
||||
.y(PCNextFSpill));
|
||||
mux2 #(`XLEN) pcspillmux(.d0(PCF), .d1(PCPlus2F), .s(SelSpillF), .y(PCFSpill));
|
||||
|
||||
@ -69,7 +69,7 @@ module spillsupport #(parameter CACHE_ENABLED)
|
||||
assign TakeSpillF = SpillF & ~IFUCacheBusStallF & ~(ITLBMissF | (`HPTW_WRITES_SUPPORTED & InstrDAPageFaultF));
|
||||
|
||||
always_ff @(posedge clk)
|
||||
if (reset) CurrState <= #1 STATE_READY;
|
||||
if (reset | Flush) CurrState <= #1 STATE_READY;
|
||||
else CurrState <= #1 NextState;
|
||||
|
||||
always_comb begin
|
||||
@ -89,7 +89,7 @@ module spillsupport #(parameter CACHE_ENABLED)
|
||||
assign SavedInstr = CACHE_ENABLED ? InstrRawF[15:0] : InstrRawF[31:16];
|
||||
|
||||
flopenr #(16) SpillInstrReg(.clk(clk),
|
||||
.en(SpillSaveF),
|
||||
.en(SpillSaveF & ~Flush),
|
||||
.reset(reset),
|
||||
.d(SavedInstr),
|
||||
.q(SpillDataLine0));
|
||||
|
||||
@ -30,13 +30,13 @@
|
||||
`include "wally-config.vh"
|
||||
|
||||
module dtim(
|
||||
input logic clk, reset, ce,
|
||||
input logic [1:0] MemRWM,
|
||||
input logic [`PA_BITS-1:0] Adr,
|
||||
input logic TrapM,
|
||||
input logic [`LLEN-1:0] WriteDataM,
|
||||
input logic [`LLEN/8-1:0] ByteMaskM,
|
||||
output logic [`LLEN-1:0] ReadDataWordM
|
||||
input logic clk, reset, ce,
|
||||
input logic [1:0] MemRWM,
|
||||
input logic [`PA_BITS-1:0] Adr,
|
||||
input logic FlushW,
|
||||
input logic [`LLEN-1:0] WriteDataM,
|
||||
input logic [`LLEN/8-1:0] ByteMaskM,
|
||||
output logic [`LLEN-1:0] ReadDataWordM
|
||||
);
|
||||
|
||||
logic we;
|
||||
@ -44,7 +44,7 @@ module dtim(
|
||||
localparam ADDR_WDITH = $clog2(`DTIM_RANGE/8);
|
||||
localparam OFFSET = $clog2(`LLEN/8);
|
||||
|
||||
assign we = MemRWM[0] & ~TrapM; // have to ignore write if Trap.
|
||||
assign we = MemRWM[0] & ~FlushW; // have to ignore write if Trap.
|
||||
|
||||
sram1p1rw #(.DEPTH(`DTIM_RANGE/8), .WIDTH(`LLEN))
|
||||
ram(.clk, .ce, .we, .bwe(ByteMaskM), .addr(Adr[ADDR_WDITH+OFFSET-1:OFFSET]), .dout(ReadDataWordM), .din(WriteDataM));
|
||||
|
||||
@ -47,7 +47,6 @@ module lsu (
|
||||
input logic [2:0] Funct3M,
|
||||
input logic [6:0] Funct7M,
|
||||
input logic [1:0] AtomicM,
|
||||
input logic TrapM,
|
||||
input logic FlushDCacheM,
|
||||
output logic CommittedM,
|
||||
output logic SquashSCW,
|
||||
@ -131,7 +130,7 @@ module lsu (
|
||||
if(`VIRTMEM_SUPPORTED) begin : VIRTMEM_SUPPORTED
|
||||
lsuvirtmem lsuvirtmem(.clk, .reset, .StallW, .MemRWM, .AtomicM, .ITLBMissF, .ITLBWriteF,
|
||||
.DTLBMissM, .DTLBWriteM, .InstrDAPageFaultF, .DataDAPageFaultM,
|
||||
.TrapM, .DCacheStallM, .SATP_REGW, .PCF,
|
||||
.FlushW, .DCacheStallM, .SATP_REGW, .PCF,
|
||||
.STATUS_MXR, .STATUS_SUM, .STATUS_MPRV, .STATUS_MPP, .PrivilegeModeW,
|
||||
.ReadDataM(ReadDataM[`XLEN-1:0]), .WriteDataM, .Funct3M, .LSUFunct3M, .Funct7M, .LSUFunct7M,
|
||||
.IEUAdrExtM, .PTE, .IMWriteDataM, .PageType, .PreLSURWM, .LSUAtomicM,
|
||||
@ -203,7 +202,7 @@ module lsu (
|
||||
logic [`LLEN-1:0] ReadDataWordM, LittleEndianReadDataWordM;
|
||||
logic [`LLEN-1:0] ReadDataWordMuxM, DTIMReadDataWordM, DCacheReadDataWordM;
|
||||
logic IgnoreRequest;
|
||||
assign IgnoreRequest = IgnoreRequestTLB | TrapM;
|
||||
assign IgnoreRequest = IgnoreRequestTLB | FlushW;
|
||||
|
||||
if (`DTIM_SUPPORTED) begin : dtim
|
||||
logic [`PA_BITS-1:0] DTIMAdr;
|
||||
@ -211,12 +210,12 @@ module lsu (
|
||||
|
||||
// The DTIM uses untranslated addresses, so it is not compatible with virtual memory.
|
||||
assign DTIMAdr = MemRWM[0] ? IEUAdrExtM[`PA_BITS-1:0] : IEUAdrExtE[`PA_BITS-1:0]; // zero extend or contract to PA_BITS
|
||||
assign DTIMMemRWM = SelDTIM & ~IgnoreRequest ? LSURWM : '0;
|
||||
assign DTIMMemRWM = SelDTIM & ~IgnoreRequestTLB ? LSURWM : '0;
|
||||
// **** fix ReadDataWordM to be LLEN. ByteMask is wrong length.
|
||||
// **** create config to support DTIM with floating point.
|
||||
dtim dtim(.clk, .reset, .ce(~CPUBusy), .MemRWM(DTIMMemRWM),
|
||||
.Adr(DTIMAdr),
|
||||
.TrapM, .WriteDataM(LSUWriteDataM),
|
||||
.FlushW, .WriteDataM(LSUWriteDataM),
|
||||
.ReadDataWordM(DTIMReadDataWordM[`XLEN-1:0]), .ByteMaskM(ByteMaskM[`XLEN/8-1:0]));
|
||||
end else begin
|
||||
end
|
||||
@ -242,15 +241,15 @@ module lsu (
|
||||
logic [1:0] CacheRWM, CacheAtomicM;
|
||||
logic CacheFlushM;
|
||||
|
||||
assign BusRW = ~CacheableM & ~IgnoreRequest & ~SelDTIM ? LSURWM : '0;
|
||||
assign BusRW = ~CacheableM & ~IgnoreRequestTLB & ~SelDTIM ? LSURWM : '0;
|
||||
assign CacheableOrFlushCacheM = CacheableM | FlushDCacheM;
|
||||
assign CacheRWM = CacheableM & ~IgnoreRequest & ~SelDTIM ? LSURWM : '0;
|
||||
assign CacheAtomicM = CacheableM & ~IgnoreRequest & ~SelDTIM ? LSUAtomicM : '0;
|
||||
assign CacheFlushM = ~TrapM & FlushDCacheM;
|
||||
assign CacheRWM = CacheableM & ~IgnoreRequestTLB & ~SelDTIM ? LSURWM : '0;
|
||||
assign CacheAtomicM = CacheableM & ~IgnoreRequestTLB & ~SelDTIM ? LSUAtomicM : '0;
|
||||
assign CacheFlushM = FlushDCacheM;
|
||||
|
||||
cache #(.LINELEN(`DCACHE_LINELENINBITS), .NUMLINES(`DCACHE_WAYSIZEINBYTES*8/LINELEN),
|
||||
.NUMWAYS(`DCACHE_NUMWAYS), .LOGBWPL(LLENLOGBWPL), .WORDLEN(`LLEN), .MUXINTERVAL(`LLEN), .DCACHE(1)) dcache(
|
||||
.clk, .reset, .CPUBusy, .SelBusWord, .CacheRW(CacheRWM), .CacheAtomic(CacheAtomicM),
|
||||
.clk, .reset, .CPUBusy, .SelBusWord, .Flush(FlushW), .CacheRW(CacheRWM), .CacheAtomic(CacheAtomicM),
|
||||
.FlushCache(CacheFlushM), .NextAdr(IEUAdrE[11:0]), .PAdr(PAdrM),
|
||||
.ByteMask(ByteMaskM), .WordCount(WordCount[AHBWLOGBWPL-1:AHBWLOGBWPL-LLENLOGBWPL]),
|
||||
.FinalWriteData(LSUWriteDataM), .SelHPTW,
|
||||
@ -260,7 +259,7 @@ module lsu (
|
||||
.FetchBuffer, .CacheBusRW,
|
||||
.CacheBusAck(DCacheBusAck), .InvalidateCache(1'b0));
|
||||
ahbcacheinterface #(.WORDSPERLINE(AHBWWORDSPERLINE), .LINELEN(LINELEN), .LOGWPL(AHBWLOGBWPL), .CACHE_ENABLED(`DCACHE)) ahbcacheinterface(
|
||||
.HCLK(clk), .HRESETn(~reset),
|
||||
.HCLK(clk), .HRESETn(~reset), .Flush(FlushW),
|
||||
.HRDATA,
|
||||
.HSIZE(LSUHSIZE), .HBURST(LSUHBURST), .HTRANS(LSUHTRANS), .HWRITE(LSUHWRITE), .HREADY(LSUHREADY),
|
||||
.WordCount, .SelBusWord,
|
||||
@ -303,13 +302,13 @@ module lsu (
|
||||
logic CaptureEn;
|
||||
logic [1:0] BusRW;
|
||||
logic [`XLEN-1:0] FetchBuffer;
|
||||
assign BusRW = ~IgnoreRequest & ~SelDTIM ? LSURWM : '0;
|
||||
assign BusRW = ~IgnoreRequestTLB & ~SelDTIM ? LSURWM : '0;
|
||||
// assign BusRW = LSURWM & ~{IgnoreRequest, IgnoreRequest} & ~{SelDTIM, SelDTIM};
|
||||
|
||||
assign LSUHADDR = PAdrM;
|
||||
assign LSUHSIZE = LSUFunct3M;
|
||||
|
||||
ahbinterface #(1) ahbinterface(.HCLK(clk), .HRESETn(~reset), .HREADY(LSUHREADY),
|
||||
ahbinterface #(1) ahbinterface(.HCLK(clk), .HRESETn(~reset), .Flush(FlushW), .HREADY(LSUHREADY),
|
||||
.HRDATA(HRDATA), .HTRANS(LSUHTRANS), .HWRITE(LSUHWRITE), .HWDATA(LSUHWDATA),
|
||||
.HWSTRB(LSUHWSTRB), .BusRW, .ByteMask(ByteMaskM), .WriteData(LSUWriteDataM),
|
||||
.CPUBusy, .BusStall, .BusCommitted(BusCommittedM), .FetchBuffer(FetchBuffer));
|
||||
|
||||
@ -39,7 +39,7 @@ module lsuvirtmem(
|
||||
output logic DTLBWriteM,
|
||||
input logic InstrDAPageFaultF,
|
||||
input logic DataDAPageFaultM,
|
||||
input logic TrapM,
|
||||
input logic FlushW,
|
||||
input logic DCacheStallM,
|
||||
input logic [`XLEN-1:0] SATP_REGW, // from csr
|
||||
input logic STATUS_MXR, STATUS_SUM, STATUS_MPRV,
|
||||
@ -80,11 +80,13 @@ module lsuvirtmem(
|
||||
// move all the muxes to walkermux and instantiate these in lsu under virtmem_supported.
|
||||
assign ITLBMissOrDAFaultF = ITLBMissF | (`HPTW_WRITES_SUPPORTED & InstrDAPageFaultF);
|
||||
assign DTLBMissOrDAFaultM = DTLBMissM | (`HPTW_WRITES_SUPPORTED & DataDAPageFaultM);
|
||||
assign ITLBMissOrDAFaultNoTrapF = ITLBMissOrDAFaultF & ~TrapM;
|
||||
assign DTLBMissOrDAFaultNoTrapM = DTLBMissOrDAFaultM & ~TrapM;
|
||||
//assign ITLBMissOrDAFaultNoTrapF = ITLBMissOrDAFaultF & ~TrapM;
|
||||
assign ITLBMissOrDAFaultNoTrapF = ITLBMissOrDAFaultF;
|
||||
//assign DTLBMissOrDAFaultNoTrapM = DTLBMissOrDAFaultM & ~TrapM;
|
||||
assign DTLBMissOrDAFaultNoTrapM = DTLBMissOrDAFaultM;
|
||||
|
||||
hptw hptw(
|
||||
.clk, .reset, .SATP_REGW, .PCF, .IEUAdrExtM, .MemRWM, .AtomicM,
|
||||
.clk, .reset, .SATP_REGW, .PCF, .IEUAdrExtM, .MemRWM, .AtomicM, .FlushW,
|
||||
.STATUS_MXR, .STATUS_SUM, .STATUS_MPRV, .STATUS_MPP, .PrivilegeModeW,
|
||||
.ITLBMissOrDAFaultNoTrapF, .DTLBMissOrDAFaultNoTrapM,
|
||||
.PTE, .PageType, .ITLBWriteF, .DTLBWriteM, .HPTWReadPTE(ReadDataM), // *** should it be HPTWReadDataM
|
||||
|
||||
@ -37,6 +37,7 @@ module hptw
|
||||
input logic [`XLEN-1:0] PCF, // addresses to translate
|
||||
input logic [`XLEN+1:0] IEUAdrExtM, // addresses to translate
|
||||
input logic [1:0] MemRWM, AtomicM,
|
||||
input logic FlushW,
|
||||
// system status
|
||||
input logic STATUS_MXR, STATUS_SUM, STATUS_MPRV,
|
||||
input logic [1:0] STATUS_MPP,
|
||||
@ -217,7 +218,14 @@ module hptw
|
||||
end
|
||||
|
||||
// Page Table Walker FSM
|
||||
flopenl #(.TYPE(statetype)) WalkerStateReg(clk, reset, 1'b1, NextWalkerState, IDLE, WalkerState);
|
||||
// there is a bug here. Each memory access needs to be potentially flushed if the PMA/P checkers
|
||||
// generate an access fault. Specially the store on UDPATE_PTE needs to check for access violation.
|
||||
// I think the solution is to do 1 of the following
|
||||
// 1. Allow the HPTW to generate exceptions and stop walking immediately.
|
||||
// 2. If the store would generate an exception don't store to dcache but still write the TLB. When we go back
|
||||
// to LEAF then the PMA/P. Wait this does not work. The PMA/P won't be looking a the address in the table, but
|
||||
// rather than physical address of the translated instruction/data. So we must generate the exception.
|
||||
flopenl #(.TYPE(statetype)) WalkerStateReg(clk, reset | FlushW, 1'b1, NextWalkerState, IDLE, WalkerState);
|
||||
always_comb
|
||||
case (WalkerState)
|
||||
IDLE: if (TLBMiss) NextWalkerState = InitialWalkerState;
|
||||
@ -250,3 +258,7 @@ module hptw
|
||||
assign HPTWStall = (WalkerState != IDLE) | (WalkerState == IDLE & TLBMiss);
|
||||
|
||||
endmodule
|
||||
|
||||
// another idea. We keep gating the control by ~TrapM, but this adds considerable length to the critical path.
|
||||
// should we do this differently? For example TLBMiss is gated by ~TrapM and then drives HPTWStall, which drives LSUStallM, which drives
|
||||
// the hazard unit to issue stall and flush controlls. ~TrapM already suppresses these in the hazard unit.
|
||||
|
||||
@ -170,7 +170,7 @@ module wallypipelinedcore (
|
||||
ifu ifu(
|
||||
.clk, .reset,
|
||||
.StallF, .StallD, .StallE, .StallM,
|
||||
.FlushF, .FlushD, .FlushE, .FlushM,
|
||||
.FlushF, .FlushD, .FlushE, .FlushM, .FlushW,
|
||||
// Fetch
|
||||
.HRDATA, .PCF, .IFUHADDR,
|
||||
.IFUStallF, .IFUHBURST, .IFUHTRANS, .IFUHSIZE,
|
||||
@ -249,7 +249,7 @@ module wallypipelinedcore (
|
||||
.FlushW,
|
||||
// CPU interface
|
||||
.MemRWM, .Funct3M, .Funct7M(InstrM[31:25]),
|
||||
.AtomicM, .TrapM,
|
||||
.AtomicM,
|
||||
.CommittedM, .DCacheMiss, .DCacheAccess,
|
||||
.SquashSCW,
|
||||
.FpLoadStoreM,
|
||||
|
||||
Loading…
Reference in New Issue
Block a user