Removed CacheBusAck

pipelined/src/lsu/busfsm.sv

@@ -49,7 +49,6 @@ module busfsm #(parameter integer LOGWPL)
    output logic [2:0]        HBURST,
    output logic              BusTransComplete,
    output logic [1:0]        HTRANS,
-   output logic              CacheBusAck,
    output logic              BusCommitted,
    output logic              BufferCaptureEn);
   
@@ -123,6 +122,5 @@ module busfsm #(parameter integer LOGWPL)
   // Makes bus only do uncached reads/writes when we actually do uncached reads/writes. Needed because Cacheable is 0 when flushing cache.
   assign UnCachedRW = UnCachedBusWrite | UnCachedBusRead; 
 
-  assign CacheBusAck = 0;
-  assign BusCommitted = BusCurrState != STATE_BUS_READY;
+   assign BusCommitted = BusCurrState != STATE_BUS_READY;
 endmodule

pipelined/src/lsu/lsu.sv

@@ -220,11 +220,10 @@ module lsu (
     logic [`PA_BITS-1:0] DCacheBusAdr;
     logic                DCacheWriteLine;
     logic                DCacheFetchLine;
-    logic                DCacheBusAck;
     logic [LOGBWPL-1:0]   WordCount;
             
     if(`DCACHE) begin : dcache
-      logic                SelUncachedAdr;
+      logic                SelUncachedAdr, DCacheBusAck;
 
       cache #(.LINELEN(`DCACHE_LINELENINBITS), .NUMLINES(`DCACHE_WAYSIZEINBYTES*8/LINELEN),
               .NUMWAYS(`DCACHE_NUMWAYS), .LOGBWPL(LOGBWPL), .WORDLEN(`LLEN), .MUXINTERVAL(`XLEN), .DCACHE(1)) dcache(
@@ -262,7 +261,7 @@ module lsu (
         .BusAck(LSUBusAck), .BusInit(LSUBusInit), .CPUBusy, .Cacheable(1'b0), .BusStall, .BusWrite(LSUBusWrite), 
         .SelBusWord, .BusRead(LSUBusRead), .BufferCaptureEn,
         .HBURST(LSUHBURST), .HTRANS(LSUHTRANS), .BusTransComplete(LSUTransComplete), 
-        .CacheBusAck(DCacheBusAck), .BusCommitted(BusCommittedM));
+        .BusCommitted(BusCommittedM));
     
       // *** possible bug - ReadDatWordM vs. ReadDataWordMuxW - is byte swapping needed for endian
       assign {ReadDataWordM, DCacheStallM, DCacheCommittedM, DCacheFetchLine, DCacheWriteLine} = '0;