forked from Github_Repos/cvw
Merge pull request #187 from stineje/main
Update one bug in testfloat - still have to fix fpdiv but others shou…
This commit is contained in:
David Harris
GitHub
commit
fc158fd6e5
@ -1,7 +1,8 @@
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///////////////////////////////////////////
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<///////////////////////////////////////////
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//
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// Written: me@KatherineParry.com
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// Modified: 7/5/2022
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// Modified: 4/2/2023
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//
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// Purpose: Testbench for Testfloat
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//
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@ -32,75 +33,74 @@
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module testbenchfp;
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parameter TEST="none";
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string Tests[]; // list of tests to be run
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logic [2:0] OpCtrl[]; // list of op controls
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logic [2:0] Unit[]; // list of units being tested
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logic WriteInt[]; // Is being written to integer resgiter
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logic [2:0] Frm[4:0] = {3'b100, 3'b010, 3'b011, 3'b001, 3'b000}; // rounding modes: rne-000, rz-001, ru-011, rd-010, rnm-100
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logic [1:0] Fmt[]; // list of formats for the other units
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string Tests[]; // list of tests to be run
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logic [2:0] OpCtrl[]; // list of op controls
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logic [2:0] Unit[]; // list of units being tested
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logic WriteInt[]; // Is being written to integer resgiter
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logic [2:0] Frm[4:0] = {3'b100, 3'b010, 3'b011, 3'b001, 3'b000}; // rounding modes: rne-000, rz-001, ru-011, rd-010, rnm-100
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logic [1:0] Fmt[]; // list of formats for the other units
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logic clk=0;
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logic [31:0] TestNum=0; // index for the test
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logic [31:0] OpCtrlNum=0; // index for OpCtrl
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logic [31:0] errors=0; // how many errors
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logic [31:0] VectorNum=0; // index for test vector
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logic [31:0] FrmNum=0; // index for rounding mode
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logic [`FLEN*4+7:0] TestVectors[8388609:0]; // list of test vectors
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logic clk=0;
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logic [31:0] TestNum=0; // index for the test
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logic [31:0] OpCtrlNum=0; // index for OpCtrl
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logic [31:0] errors=0; // how many errors
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logic [31:0] VectorNum=0; // index for test vector
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logic [31:0] FrmNum=0; // index for rounding mode
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logic [`FLEN*4+7:0] TestVectors[8388609:0]; // list of test vectors
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logic [1:0] FmtVal; // value of the current Fmt
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logic [2:0] UnitVal, OpCtrlVal, FrmVal; // value of the currnet Unit/OpCtrl/FrmVal
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logic WriteIntVal; // value of the current WriteInt
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logic [`FLEN-1:0] X, Y, Z; // inputs read from TestFloat
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logic [`XLEN-1:0] SrcA; // integer input
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logic [`FLEN-1:0] Ans; // correct answer from TestFloat
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logic [`FLEN-1:0] Res; // result from other units
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logic [4:0] AnsFlg; // correct flags read from testfloat
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logic [4:0] ResFlg, Flg; // Result flags
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logic [`FMTBITS-1:0] ModFmt; // format - 10 = half, 00 = single, 01 = double, 11 = quad
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logic [`FLEN-1:0] FpRes, FpCmpRes; // Results from each unit
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logic [`XLEN-1:0] IntRes, CmpRes; // Results from each unit
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logic [4:0] FmaFlg, CvtFlg, DivFlg, CmpFlg; // Outputed flags
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logic AnsNaN, ResNaN, NaNGood;
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logic Xs, Ys, Zs; // sign of the inputs
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logic [`NE-1:0] Xe, Ye, Ze; // exponent of the inputs
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logic [`NF:0] Xm, Ym, Zm; // mantissas of the inputs
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logic XNaN, YNaN, ZNaN; // is the input NaN
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logic XSNaN, YSNaN, ZSNaN; // is the input a signaling NaN
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logic XSubnorm, ZSubnorm; // is the input denormalized
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logic XInf, YInf, ZInf; // is the input infinity
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logic XZero, YZero, ZZero; // is the input zero
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logic XExpMax, YExpMax, ZExpMax; // is the input's exponent all ones
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logic [`CVTLEN-1:0] CvtLzcInE; // input to the Leading Zero Counter (priority encoder)
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logic IntZero;
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logic CvtResSgnE;
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logic [`NE:0] CvtCalcExpE; // the calculated expoent
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logic [`LOGCVTLEN-1:0] CvtShiftAmtE; // how much to shift by
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logic [`DIVb:0] Quot;
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logic CvtResSubnormUfE;
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logic DivStart, FDivBusyE, OldFDivBusyE;
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logic reset = 1'b0;
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logic [$clog2(`NF+2)-1:0] XZeroCnt, YZeroCnt;
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logic [`DURLEN-1:0] Dur;
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logic [1:0] FmtVal; // value of the current Fmt
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logic [2:0] UnitVal, OpCtrlVal, FrmVal; // value of the currnet Unit/OpCtrl/FrmVal
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logic WriteIntVal; // value of the current WriteInt
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logic [`FLEN-1:0] X, Y, Z; // inputs read from TestFloat
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logic [`XLEN-1:0] SrcA; // integer input
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logic [`FLEN-1:0] Ans; // correct answer from TestFloat
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logic [`FLEN-1:0] Res; // result from other units
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logic [4:0] AnsFlg; // correct flags read from testfloat
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logic [4:0] ResFlg, Flg; // Result flags
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logic [`FMTBITS-1:0] ModFmt; // format - 10 = half, 00 = single, 01 = double, 11 = quad
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logic [`FLEN-1:0] FpRes, FpCmpRes; // Results from each unit
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logic [`XLEN-1:0] IntRes, CmpRes; // Results from each unit
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logic [4:0] FmaFlg, CvtFlg, DivFlg, CmpFlg; // Outputed flags
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logic AnsNaN, ResNaN, NaNGood;
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logic Xs, Ys, Zs; // sign of the inputs
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logic [`NE-1:0] Xe, Ye, Ze; // exponent of the inputs
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logic [`NF:0] Xm, Ym, Zm; // mantissas of the inputs
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logic XNaN, YNaN, ZNaN; // is the input NaN
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logic XSNaN, YSNaN, ZSNaN; // is the input a signaling NaN
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logic XSubnorm, ZSubnorm; // is the input denormalized
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logic XInf, YInf, ZInf; // is the input infinity
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logic XZero, YZero, ZZero; // is the input zero
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logic XExpMax, YExpMax, ZExpMax; // is the input's exponent all ones
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logic [`CVTLEN-1:0] CvtLzcInE; // input to the Leading Zero Counter (priority encoder)
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logic IntZero;
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logic CvtResSgnE;
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logic [`NE:0] CvtCalcExpE; // the calculated expoent
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logic [`LOGCVTLEN-1:0] CvtShiftAmtE; // how much to shift by
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logic [`DIVb:0] Quot;
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logic CvtResSubnormUfE;
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logic DivStart, FDivBusyE, OldFDivBusyE;
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logic reset = 1'b0;
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logic [$clog2(`NF+2)-1:0] XZeroCnt, YZeroCnt;
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logic [`DURLEN-1:0] Dur;
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// in-between FMA signals
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logic Mult;
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logic Ss;
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logic [`NE+1:0] Pe;
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logic [`NE+1:0] Se;
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logic ASticky;
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logic KillProd;
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logic [$clog2(3*`NF+5)-1:0] SCnt;
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logic [3*`NF+3:0] Sm;
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logic InvA;
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logic NegSum;
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logic As;
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logic Ps;
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logic DivSticky;
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logic DivDone;
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logic DivNegSticky;
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logic [`NE+1:0] DivCalcExp;
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logic divsqrtop;
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logic Mult;
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logic Ss;
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logic [`NE+1:0] Pe;
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logic [`NE+1:0] Se;
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logic ASticky;
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logic KillProd;
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logic [$clog2(3*`NF+5)-1:0] SCnt;
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logic [3*`NF+3:0] Sm;
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logic InvA;
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logic NegSum;
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logic As;
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logic Ps;
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logic DivSticky;
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logic DivDone;
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logic DivNegSticky;
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logic [`NE+1:0] DivCalcExp;
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logic divsqrtop;
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///////////////////////////////////////////////////////////////////////////////////////////////
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@ -126,28 +126,28 @@ module testbenchfp;
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$display("TEST is %s", TEST);
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if (`Q_SUPPORTED) begin // if Quad percision is supported
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if (TEST === "cvtint"| TEST === "all") begin // if testing integer conversion
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// add the 128-bit cvtint tests to the to-be-tested list
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Tests = {Tests, f128rv32cvtint};
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// add the op-codes for these tests to the op-code list
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OpCtrl = {OpCtrl, `FROM_UI_OPCTRL, `FROM_I_OPCTRL, `TO_UI_OPCTRL, `TO_I_OPCTRL};
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WriteInt = {WriteInt, 1'b0, 1'b0, 1'b1, 1'b1};
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// add what unit is used and the fmt to their lists (one for each test)
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for(int i = 0; i<20; i++) begin
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Unit = {Unit, `CVTINTUNIT};
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Fmt = {Fmt, 2'b11};
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end
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if (`XLEN == 64) begin // if 64-bit integers are supported add their conversions
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Tests = {Tests, f128rv64cvtint};
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// add the op-codes for these tests to the op-code list
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OpCtrl = {OpCtrl, `FROM_UL_OPCTRL, `FROM_L_OPCTRL, `TO_UL_OPCTRL, `TO_L_OPCTRL};
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WriteInt = {WriteInt, 1'b0, 1'b0, 1'b1, 1'b1};
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// add what unit is used and the fmt to their lists (one for each test)
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for(int i = 0; i<20; i++) begin
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Unit = {Unit, `CVTINTUNIT};
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Fmt = {Fmt, 2'b11};
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end
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end
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end
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// add the 128-bit cvtint tests to the to-be-tested list
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Tests = {Tests, f128rv32cvtint};
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// add the op-codes for these tests to the op-code list
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OpCtrl = {OpCtrl, `FROM_UI_OPCTRL, `FROM_I_OPCTRL, `TO_UI_OPCTRL, `TO_I_OPCTRL};
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WriteInt = {WriteInt, 1'b0, 1'b0, 1'b1, 1'b1};
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// add what unit is used and the fmt to their lists (one for each test)
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for(int i = 0; i<20; i++) begin
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Unit = {Unit, `CVTINTUNIT};
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Fmt = {Fmt, 2'b11};
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end
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if (`XLEN == 64) begin // if 64-bit integers are supported add their conversions
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Tests = {Tests, f128rv64cvtint};
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// add the op-codes for these tests to the op-code list
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OpCtrl = {OpCtrl, `FROM_UL_OPCTRL, `FROM_L_OPCTRL, `TO_UL_OPCTRL, `TO_L_OPCTRL};
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WriteInt = {WriteInt, 1'b0, 1'b0, 1'b1, 1'b1};
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// add what unit is used and the fmt to their lists (one for each test)
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for(int i = 0; i<20; i++) begin
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Unit = {Unit, `CVTINTUNIT};
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Fmt = {Fmt, 2'b11};
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end
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end
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end
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if (TEST === "cvtfp" | TEST === "all") begin // if the floating-point conversions are being tested
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if(`D_SUPPORTED) begin // if double precision is supported
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// add the 128 <-> 64 bit conversions to the to-be-tested list
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@ -270,27 +270,27 @@ module testbenchfp;
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end
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if (`D_SUPPORTED) begin // if double precision is supported
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if (TEST === "cvtint"| TEST === "all") begin // if integer conversion is being tested
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Tests = {Tests, f64rv32cvtint};
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// add the op-codes for these tests to the op-code list
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OpCtrl = {OpCtrl, `FROM_UI_OPCTRL, `FROM_I_OPCTRL, `TO_UI_OPCTRL, `TO_I_OPCTRL};
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WriteInt = {WriteInt, 1'b0, 1'b0, 1'b1, 1'b1};
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// add what unit is used and the fmt to their lists (one for each test)
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for(int i = 0; i<20; i++) begin
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Unit = {Unit, `CVTINTUNIT};
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Fmt = {Fmt, 2'b01};
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end
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if (`XLEN == 64) begin // if 64-bit integers are being supported
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Tests = {Tests, f64rv64cvtint};
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// add the op-codes for these tests to the op-code list
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OpCtrl = {OpCtrl, `FROM_UL_OPCTRL, `FROM_L_OPCTRL, `TO_UL_OPCTRL, `TO_L_OPCTRL};
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WriteInt = {WriteInt, 1'b0, 1'b0, 1'b1, 1'b1};
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// add what unit is used and the fmt to their lists (one for each test)
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for(int i = 0; i<20; i++) begin
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Unit = {Unit, `CVTINTUNIT};
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Fmt = {Fmt, 2'b01};
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end
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end
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end
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Tests = {Tests, f64rv32cvtint};
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// add the op-codes for these tests to the op-code list
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OpCtrl = {OpCtrl, `FROM_UI_OPCTRL, `FROM_I_OPCTRL, `TO_UI_OPCTRL, `TO_I_OPCTRL};
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WriteInt = {WriteInt, 1'b0, 1'b0, 1'b1, 1'b1};
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// add what unit is used and the fmt to their lists (one for each test)
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for(int i = 0; i<20; i++) begin
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Unit = {Unit, `CVTINTUNIT};
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Fmt = {Fmt, 2'b01};
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end
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if (`XLEN == 64) begin // if 64-bit integers are being supported
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Tests = {Tests, f64rv64cvtint};
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// add the op-codes for these tests to the op-code list
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OpCtrl = {OpCtrl, `FROM_UL_OPCTRL, `FROM_L_OPCTRL, `TO_UL_OPCTRL, `TO_L_OPCTRL};
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WriteInt = {WriteInt, 1'b0, 1'b0, 1'b1, 1'b1};
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// add what unit is used and the fmt to their lists (one for each test)
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for(int i = 0; i<20; i++) begin
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Unit = {Unit, `CVTINTUNIT};
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Fmt = {Fmt, 2'b01};
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end
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end
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end
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if (TEST === "cvtfp" | TEST === "all") begin // if floating point conversions are being tested
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if(`F_SUPPORTED) begin // if single precision is supported
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// add the 64 <-> 32 bit conversions to the to-be-tested list
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@ -397,27 +397,27 @@ module testbenchfp;
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end
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if (`F_SUPPORTED) begin // if single precision being supported
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if (TEST === "cvtint"| TEST === "all") begin // if integer conversion is being tested
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Tests = {Tests, f32rv32cvtint};
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// add the op-codes for these tests to the op-code list
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OpCtrl = {OpCtrl, `FROM_UI_OPCTRL, `FROM_I_OPCTRL, `TO_UI_OPCTRL, `TO_I_OPCTRL};
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WriteInt = {WriteInt, 1'b0, 1'b0, 1'b1, 1'b1};
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// add what unit is used and the fmt to their lists (one for each test)
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for(int i = 0; i<20; i++) begin
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Unit = {Unit, `CVTINTUNIT};
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Fmt = {Fmt, 2'b00};
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end
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if (`XLEN == 64) begin // if 64-bit integers are supported
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Tests = {Tests, f32rv64cvtint};
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// add the op-codes for these tests to the op-code list
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OpCtrl = {OpCtrl, `FROM_UL_OPCTRL, `FROM_L_OPCTRL, `TO_UL_OPCTRL, `TO_L_OPCTRL};
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WriteInt = {WriteInt, 1'b0, 1'b0, 1'b1, 1'b1};
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// add what unit is used and the fmt to their lists (one for each test)
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for(int i = 0; i<20; i++) begin
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Unit = {Unit, `CVTINTUNIT};
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Fmt = {Fmt, 2'b00};
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end
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end
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end
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Tests = {Tests, f32rv32cvtint};
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// add the op-codes for these tests to the op-code list
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OpCtrl = {OpCtrl, `FROM_UI_OPCTRL, `FROM_I_OPCTRL, `TO_UI_OPCTRL, `TO_I_OPCTRL};
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WriteInt = {WriteInt, 1'b0, 1'b0, 1'b1, 1'b1};
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// add what unit is used and the fmt to their lists (one for each test)
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for(int i = 0; i<20; i++) begin
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Unit = {Unit, `CVTINTUNIT};
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Fmt = {Fmt, 2'b00};
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end
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if (`XLEN == 64) begin // if 64-bit integers are supported
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Tests = {Tests, f32rv64cvtint};
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// add the op-codes for these tests to the op-code list
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OpCtrl = {OpCtrl, `FROM_UL_OPCTRL, `FROM_L_OPCTRL, `TO_UL_OPCTRL, `TO_L_OPCTRL};
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WriteInt = {WriteInt, 1'b0, 1'b0, 1'b1, 1'b1};
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// add what unit is used and the fmt to their lists (one for each test)
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for(int i = 0; i<20; i++) begin
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Unit = {Unit, `CVTINTUNIT};
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Fmt = {Fmt, 2'b00};
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end
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end
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end
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if (TEST === "cvtfp" | TEST === "all") begin // if floating point conversion is being tested
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if(`ZFH_SUPPORTED) begin
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// add the 32 <-> 16 bit conversions to the to-be-tested list
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@ -508,27 +508,27 @@ module testbenchfp;
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end
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if (`ZFH_SUPPORTED) begin // if half precision supported
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if (TEST === "cvtint"| TEST === "all") begin // if in conversions are being tested
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Tests = {Tests, f16rv32cvtint};
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// add the op-codes for these tests to the op-code list
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OpCtrl = {OpCtrl, `FROM_UI_OPCTRL, `FROM_I_OPCTRL, `TO_UI_OPCTRL, `TO_I_OPCTRL};
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WriteInt = {WriteInt, 1'b0, 1'b0, 1'b1, 1'b1};
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// add what unit is used and the fmt to their lists (one for each test)
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for(int i = 0; i<20; i++) begin
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Unit = {Unit, `CVTINTUNIT};
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Fmt = {Fmt, 2'b10};
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end
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if (`XLEN == 64) begin // if 64-bit integers are supported
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Tests = {Tests, f16rv64cvtint};
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// add the op-codes for these tests to the op-code list
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OpCtrl = {OpCtrl, `FROM_UL_OPCTRL, `FROM_L_OPCTRL, `TO_UL_OPCTRL, `TO_L_OPCTRL};
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WriteInt = {WriteInt, 1'b0, 1'b0, 1'b1, 1'b1};
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// add what unit is used and the fmt to their lists (one for each test)
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for(int i = 0; i<20; i++) begin
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Unit = {Unit, `CVTINTUNIT};
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Fmt = {Fmt, 2'b10};
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end
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end
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end
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Tests = {Tests, f16rv32cvtint};
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// add the op-codes for these tests to the op-code list
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OpCtrl = {OpCtrl, `FROM_UI_OPCTRL, `FROM_I_OPCTRL, `TO_UI_OPCTRL, `TO_I_OPCTRL};
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WriteInt = {WriteInt, 1'b0, 1'b0, 1'b1, 1'b1};
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// add what unit is used and the fmt to their lists (one for each test)
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for(int i = 0; i<20; i++) begin
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Unit = {Unit, `CVTINTUNIT};
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Fmt = {Fmt, 2'b10};
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end
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if (`XLEN == 64) begin // if 64-bit integers are supported
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Tests = {Tests, f16rv64cvtint};
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// add the op-codes for these tests to the op-code list
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OpCtrl = {OpCtrl, `FROM_UL_OPCTRL, `FROM_L_OPCTRL, `TO_UL_OPCTRL, `TO_L_OPCTRL};
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WriteInt = {WriteInt, 1'b0, 1'b0, 1'b1, 1'b1};
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// add what unit is used and the fmt to their lists (one for each test)
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for(int i = 0; i<20; i++) begin
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Unit = {Unit, `CVTINTUNIT};
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Fmt = {Fmt, 2'b10};
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end
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end
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end
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||||
if (TEST === "cmp" | TEST === "all") begin // if comparisions are being tested
|
||||
// add the correct tests/op-ctrls/unit/fmt to their lists
|
||||
Tests = {Tests, f16cmp};
|
||||
@ -656,7 +656,8 @@ module testbenchfp;
|
||||
end
|
||||
|
||||
// extract the inputs (X, Y, Z, SrcA) and the output (Ans, AnsFlg) from the current test vector
|
||||
readvectors readvectors (.clk, .Fmt(FmtVal), .ModFmt, .TestVector(TestVectors[VectorNum]), .VectorNum, .Ans(Ans), .AnsFlg(AnsFlg), .SrcA,
|
||||
readvectors readvectors (.clk, .Fmt(FmtVal), .ModFmt, .TestVector(TestVectors[VectorNum]),
|
||||
.VectorNum, .Ans(Ans), .AnsFlg(AnsFlg), .SrcA,
|
||||
.Xs, .Ys, .Zs, .Unit(UnitVal),
|
||||
.Xe, .Ye, .Ze, .TestNum, .OpCtrl(OpCtrlVal),
|
||||
.Xm, .Ym, .Zm, .DivStart,
|
||||
@ -680,7 +681,7 @@ module testbenchfp;
|
||||
///////////////////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
// instantiate devices under test
|
||||
if (TEST === "fma"| TEST === "mul" | TEST === "add" | TEST === "all") begin : fma
|
||||
if (TEST === "fma"| TEST === "mul" | TEST === "add" | TEST === "sub" | TEST === "all") begin : fma
|
||||
fma fma(.Xs(Xs), .Ys(Ys), .Zs(Zs),
|
||||
.Xe(Xe), .Ye(Ye), .Ze(Ze),
|
||||
.Xm(Xm), .Ym(Ym), .Zm(Zm),
|
||||
@ -1331,4 +1332,4 @@ module readvectors (
|
||||
.Xm, .Ym, .Zm, .XNaN, .YNaN, .ZNaN, .XSNaN, .YSNaN, .ZSNaN,
|
||||
.XSubnorm, .XZero, .YZero, .ZZero, .XInf, .YInf, .ZInf,
|
||||
.XEn, .YEn, .ZEn, .XExpMax);
|
||||
endmodule
|
||||
endmodule
|
||||
|
||||
Loading…
Reference in New Issue
Block a user