forked from Github_Repos/cvw
Renamed Word to Beat for ahbcacheinterface.
This commit is contained in:
Ross Thompson
parent
3653d6b3ed
commit
31d5eabd77
6
pipelined/src/cache/cache.sv
vendored
6
pipelined/src/cache/cache.sv
vendored
@ -54,8 +54,8 @@ module cache #(parameter LINELEN, NUMLINES, NUMWAYS, LOGBWPL, WORDLEN, MUXINTE
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// Bus fsm interface
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output logic [1:0] CacheBusRW,
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input logic CacheBusAck,
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input logic SelBusWord,
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input logic [LOGBWPL-1:0] WordCount,
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input logic SelBusBeat,
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input logic [LOGBWPL-1:0] BeatCount,
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input logic [LINELEN-1:0] FetchBuffer,
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output logic [`PA_BITS-1:0] CacheBusAdr,
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output logic [WORDLEN-1:0] ReadDataWord);
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@ -143,7 +143,7 @@ module cache #(parameter LINELEN, NUMLINES, NUMWAYS, LOGBWPL, WORDLEN, MUXINTE
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// like to fix this.
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if(DCACHE)
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mux2 #(LOGBWPL) WordAdrrMux(.d0(PAdr[$clog2(LINELEN/8) - 1 : $clog2(MUXINTERVAL/8)]),
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.d1(WordCount), .s(SelBusWord),
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.d1(BeatCount), .s(SelBusBeat),
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.y(WordOffsetAddr));
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else assign WordOffsetAddr = PAdr[$clog2(LINELEN/8) - 1 : $clog2(MUXINTERVAL/8)];
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@ -34,7 +34,7 @@
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`include "wally-config.vh"
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module ahbcacheinterface #(parameter WORDSPERLINE, LINELEN, LOGWPL, CACHE_ENABLED)
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module ahbcacheinterface #(parameter BEATSPERLINE, LINELEN, LOGWPL, CACHE_ENABLED)
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(
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input logic HCLK, HRESETn,
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@ -46,7 +46,7 @@ module ahbcacheinterface #(parameter WORDSPERLINE, LINELEN, LOGWPL, CACHE_ENABLE
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output logic [1:0] HTRANS,
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output logic HWRITE,
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output logic [`PA_BITS-1:0] HADDR,
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output logic [LOGWPL-1:0] WordCount,
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output logic [LOGWPL-1:0] BeatCount,
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// cache interface
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input logic [`PA_BITS-1:0] CacheBusAdr,
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@ -61,30 +61,30 @@ module ahbcacheinterface #(parameter WORDSPERLINE, LINELEN, LOGWPL, CACHE_ENABLE
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input logic [1:0] BusRW,
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input logic CPUBusy,
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input logic [2:0] Funct3,
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output logic SelBusWord,
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output logic SelBusBeat,
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output logic BusStall,
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output logic BusCommitted);
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localparam integer WordCountThreshold = CACHE_ENABLED ? WORDSPERLINE - 1 : 0;
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localparam integer BeatCountThreshold = CACHE_ENABLED ? BEATSPERLINE - 1 : 0;
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logic [`PA_BITS-1:0] LocalHADDR;
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logic [LOGWPL-1:0] WordCountDelayed;
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logic [LOGWPL-1:0] BeatCountDelayed;
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logic CaptureEn;
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genvar index;
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for (index = 0; index < WORDSPERLINE; index++) begin:fetchbuffer
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logic [WORDSPERLINE-1:0] CaptureWord;
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assign CaptureWord[index] = CaptureEn & (index == WordCountDelayed);
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flopen #(`XLEN) fb(.clk(HCLK), .en(CaptureWord[index]), .d(HRDATA),
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for (index = 0; index < BEATSPERLINE; index++) begin:fetchbuffer
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logic [BEATSPERLINE-1:0] CaptureBeat;
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assign CaptureBeat[index] = CaptureEn & (index == BeatCountDelayed);
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flopen #(`XLEN) fb(.clk(HCLK), .en(CaptureBeat[index]), .d(HRDATA),
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.q(FetchBuffer[(index+1)*`XLEN-1:index*`XLEN]));
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end
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mux2 #(`PA_BITS) localadrmux(PAdr, CacheBusAdr, Cacheable, LocalHADDR);
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assign HADDR = ({{`PA_BITS-LOGWPL{1'b0}}, WordCount} << $clog2(`XLEN/8)) + LocalHADDR;
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assign HADDR = ({{`PA_BITS-LOGWPL{1'b0}}, BeatCount} << $clog2(`XLEN/8)) + LocalHADDR;
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mux2 #(3) sizemux(.d0(Funct3), .d1(`XLEN == 32 ? 3'b010 : 3'b011), .s(Cacheable), .y(HSIZE));
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buscachefsm #(WordCountThreshold, LOGWPL, CACHE_ENABLED) AHBBuscachefsm(
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.HCLK, .HRESETn, .Flush, .BusRW, .CPUBusy, .BusCommitted, .BusStall, .CaptureEn, .SelBusWord,
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.CacheBusRW, .CacheBusAck, .WordCount, .WordCountDelayed,
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buscachefsm #(BeatCountThreshold, LOGWPL, CACHE_ENABLED) AHBBuscachefsm(
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.HCLK, .HRESETn, .Flush, .BusRW, .CPUBusy, .BusCommitted, .BusStall, .CaptureEn, .SelBusBeat,
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.CacheBusRW, .CacheBusAck, .BeatCount, .BeatCountDelayed,
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.HREADY, .HTRANS, .HWRITE, .HBURST);
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endmodule
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@ -32,7 +32,7 @@
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`define BURST_EN 1
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// HCLK and clk must be the same clock!
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module buscachefsm #(parameter integer WordCountThreshold,
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module buscachefsm #(parameter integer BeatCountThreshold,
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parameter integer LOGWPL, parameter logic CACHE_ENABLED )
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(input logic HCLK,
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input logic HRESETn,
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@ -50,8 +50,8 @@ module buscachefsm #(parameter integer WordCountThreshold,
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output logic CacheBusAck,
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// lsu interface
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output logic [LOGWPL-1:0] WordCount, WordCountDelayed,
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output logic SelBusWord,
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output logic [LOGWPL-1:0] BeatCount, BeatCountDelayed,
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output logic SelBusBeat,
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// BUS interface
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input logic HREADY,
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@ -70,11 +70,11 @@ module buscachefsm #(parameter integer WordCountThreshold,
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(* mark_debug = "true" *) busstatetype CurrState, NextState;
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logic [LOGWPL-1:0] NextWordCount;
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logic FinalWordCount;
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logic [LOGWPL-1:0] NextBeatCount;
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logic FinalBeatCount;
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logic [2:0] LocalBurstType;
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logic WordCntEn;
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logic WordCntReset;
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logic BeatCntEn;
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logic BeatCntReset;
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logic CacheAccess;
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always_ff @(posedge HCLK)
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@ -91,13 +91,13 @@ module buscachefsm #(parameter integer WordCountThreshold,
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else NextState = DATA_PHASE;
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MEM3: if(CPUBusy) NextState = MEM3;
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else NextState = ADR_PHASE;
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CACHE_FETCH: if(HREADY & FinalWordCount & CacheBusRW[0]) NextState = CACHE_WRITEBACK;
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else if(HREADY & FinalWordCount & CacheBusRW[1]) NextState = CACHE_FETCH;
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else if(HREADY & FinalWordCount & ~|CacheBusRW) NextState = ADR_PHASE;
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CACHE_FETCH: if(HREADY & FinalBeatCount & CacheBusRW[0]) NextState = CACHE_WRITEBACK;
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else if(HREADY & FinalBeatCount & CacheBusRW[1]) NextState = CACHE_FETCH;
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else if(HREADY & FinalBeatCount & ~|CacheBusRW) NextState = ADR_PHASE;
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else NextState = CACHE_FETCH;
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CACHE_WRITEBACK: if(HREADY & FinalWordCount & CacheBusRW[0]) NextState = CACHE_WRITEBACK;
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else if(HREADY & FinalWordCount & CacheBusRW[1]) NextState = CACHE_FETCH;
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else if(HREADY & FinalWordCount & ~|CacheBusRW) NextState = ADR_PHASE;
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CACHE_WRITEBACK: if(HREADY & FinalBeatCount & CacheBusRW[0]) NextState = CACHE_WRITEBACK;
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else if(HREADY & FinalBeatCount & CacheBusRW[1]) NextState = CACHE_FETCH;
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else if(HREADY & FinalBeatCount & ~|CacheBusRW) NextState = ADR_PHASE;
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else NextState = CACHE_WRITEBACK;
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default: NextState = ADR_PHASE;
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endcase
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@ -105,25 +105,25 @@ module buscachefsm #(parameter integer WordCountThreshold,
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// IEU, LSU, and IFU controls
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flopenr #(LOGWPL)
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WordCountReg(.clk(HCLK),
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.reset(~HRESETn | WordCntReset),
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.en(WordCntEn),
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.d(NextWordCount),
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.q(WordCount));
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BeatCountReg(.clk(HCLK),
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.reset(~HRESETn | BeatCntReset),
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.en(BeatCntEn),
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.d(NextBeatCount),
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.q(BeatCount));
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// Used to store data from data phase of AHB.
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flopenr #(LOGWPL)
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WordCountDelayedReg(.clk(HCLK),
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.reset(~HRESETn | WordCntReset),
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.en(WordCntEn),
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.d(WordCount),
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.q(WordCountDelayed));
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assign NextWordCount = WordCount + 1'b1;
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BeatCountDelayedReg(.clk(HCLK),
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.reset(~HRESETn | BeatCntReset),
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.en(BeatCntEn),
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.d(BeatCount),
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.q(BeatCountDelayed));
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assign NextBeatCount = BeatCount + 1'b1;
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assign FinalWordCount = WordCountDelayed == WordCountThreshold[LOGWPL-1:0];
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assign WordCntEn = ((NextState == CACHE_WRITEBACK | NextState == CACHE_FETCH) & HREADY & ~Flush) |
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assign FinalBeatCount = BeatCountDelayed == BeatCountThreshold[LOGWPL-1:0];
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assign BeatCntEn = ((NextState == CACHE_WRITEBACK | NextState == CACHE_FETCH) & HREADY & ~Flush) |
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(NextState == ADR_PHASE & |CacheBusRW & HREADY);
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assign WordCntReset = NextState == ADR_PHASE;
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assign BeatCntReset = NextState == ADR_PHASE;
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assign CaptureEn = (CurrState == DATA_PHASE & BusRW[1]) | (CurrState == CACHE_FETCH & HREADY);
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assign CacheAccess = CurrState == CACHE_FETCH | CurrState == CACHE_WRITEBACK;
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@ -137,14 +137,14 @@ module buscachefsm #(parameter integer WordCountThreshold,
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// AHB bus interface
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assign HTRANS = (CurrState == ADR_PHASE & HREADY & (|BusRW | |CacheBusRW) & ~Flush) |
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(CacheAccess & FinalWordCount & |CacheBusRW & HREADY) ? AHB_NONSEQ : // if we have a pipelined request
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(CacheAccess & |WordCount) ? (`BURST_EN ? AHB_SEQ : AHB_NONSEQ) : AHB_IDLE;
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(CacheAccess & FinalBeatCount & |CacheBusRW & HREADY) ? AHB_NONSEQ : // if we have a pipelined request
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(CacheAccess & |BeatCount) ? (`BURST_EN ? AHB_SEQ : AHB_NONSEQ) : AHB_IDLE;
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assign HWRITE = BusRW[0] | CacheBusRW[0] | (CurrState == CACHE_WRITEBACK & |WordCount);
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assign HBURST = `BURST_EN & (|CacheBusRW | (CacheAccess & |WordCount)) ? LocalBurstType : 3'b0;
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assign HWRITE = BusRW[0] | CacheBusRW[0] | (CurrState == CACHE_WRITEBACK & |BeatCount);
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assign HBURST = `BURST_EN & (|CacheBusRW | (CacheAccess & |BeatCount)) ? LocalBurstType : 3'b0;
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always_comb begin
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case(WordCountThreshold)
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case(BeatCountThreshold)
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0: LocalBurstType = 3'b000;
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3: LocalBurstType = 3'b011; // INCR4
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7: LocalBurstType = 3'b101; // INCR8
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@ -154,8 +154,8 @@ module buscachefsm #(parameter integer WordCountThreshold,
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end
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// communication to cache
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assign CacheBusAck = (CacheAccess & HREADY & FinalWordCount);
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assign SelBusWord = (CurrState == ADR_PHASE & (BusRW[0] | CacheBusRW[0])) |
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assign CacheBusAck = (CacheAccess & HREADY & FinalBeatCount);
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assign SelBusBeat = (CurrState == ADR_PHASE & (BusRW[0] | CacheBusRW[0])) |
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(CurrState == DATA_PHASE & BusRW[0]) |
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(CurrState == CACHE_WRITEBACK) |
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(CurrState == CACHE_FETCH);
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@ -205,6 +205,7 @@ module ifu (
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assign IFURWF = 2'b10;
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end
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if (`BUS) begin : bus
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// **** must fix words per line vs beats per line as in lsu.
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localparam integer WORDSPERLINE = `ICACHE ? `ICACHE_LINELENINBITS/`XLEN : 1;
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localparam integer LOGBWPL = `ICACHE ? $clog2(WORDSPERLINE) : 1;
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if(`ICACHE) begin : icache
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@ -227,7 +228,7 @@ module ifu (
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.ReadDataWord(ICacheInstrF),
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.SelHPTW('0),
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.CacheMiss(ICacheMiss), .CacheAccess(ICacheAccess),
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.ByteMask('0), .WordCount('0), .SelBusWord('0),
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.ByteMask('0), .BeatCount('0), .SelBusBeat('0),
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.FinalWriteData('0),
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.CacheRW(CacheRWF),
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.CacheAtomic('0), .FlushCache('0),
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@ -239,7 +240,7 @@ module ifu (
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.HRDATA,
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.Flush(FlushW), .CacheBusRW, .HSIZE(IFUHSIZE), .HBURST(IFUHBURST), .HTRANS(IFUHTRANS),
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.Funct3(3'b010), .HADDR(IFUHADDR), .HREADY(IFUHREADY), .HWRITE(IFUHWRITE), .CacheBusAdr(ICacheBusAdr),
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.WordCount(), .Cacheable(CacheableF), .SelBusWord(),
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.BeatCount(), .Cacheable(CacheableF), .SelBusBeat(),
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.CacheBusAck(ICacheBusAck),
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.FetchBuffer, .PAdr(PCPF),
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.BusRW, .CPUBusy,
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@ -222,17 +222,17 @@ module lsu (
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if (`BUS) begin : bus
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localparam integer LLENWORDSPERLINE = `DCACHE ? `DCACHE_LINELENINBITS/`LLEN : 1;
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localparam integer LLENLOGBWPL = `DCACHE ? $clog2(LLENWORDSPERLINE) : 1;
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localparam integer AHBWWORDSPERLINE = `DCACHE ? `DCACHE_LINELENINBITS/`AHBW : 1;
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localparam integer AHBWLOGBWPL = `DCACHE ? $clog2(AHBWWORDSPERLINE) : 1;
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localparam integer BEATSPERLINE = `DCACHE ? `DCACHE_LINELENINBITS/`AHBW : 1;
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localparam integer AHBWLOGBWPL = `DCACHE ? $clog2(BEATSPERLINE) : 1;
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if(`DCACHE) begin : dcache
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localparam integer LINELEN = `DCACHE ? `DCACHE_LINELENINBITS : `XLEN;
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logic [LINELEN-1:0] FetchBuffer;
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logic [`PA_BITS-1:0] DCacheBusAdr;
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logic DCacheWriteLine;
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logic DCacheFetchLine;
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logic [AHBWLOGBWPL-1:0] WordCount;
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logic [AHBWLOGBWPL-1:0] BeatCount;
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logic DCacheBusAck;
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logic SelBusWord;
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logic SelBusBeat;
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logic [`XLEN-1:0] PreHWDATA; //*** change name
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logic [`XLEN/8-1:0] ByteMaskMDelay;
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logic [1:0] CacheBusRW, BusRW;
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@ -249,20 +249,20 @@ module lsu (
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cache #(.LINELEN(`DCACHE_LINELENINBITS), .NUMLINES(`DCACHE_WAYSIZEINBYTES*8/LINELEN),
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.NUMWAYS(`DCACHE_NUMWAYS), .LOGBWPL(LLENLOGBWPL), .WORDLEN(`LLEN), .MUXINTERVAL(`LLEN), .DCACHE(1)) dcache(
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.clk, .reset, .CPUBusy, .SelBusWord, .Flush(FlushW), .CacheRW(CacheRWM), .CacheAtomic(CacheAtomicM),
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.clk, .reset, .CPUBusy, .SelBusBeat, .Flush(FlushW), .CacheRW(CacheRWM), .CacheAtomic(CacheAtomicM),
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.FlushCache(CacheFlushM), .NextAdr(IEUAdrE[11:0]), .PAdr(PAdrM),
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.ByteMask(ByteMaskM), .WordCount(WordCount[AHBWLOGBWPL-1:AHBWLOGBWPL-LLENLOGBWPL]),
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.ByteMask(ByteMaskM), .BeatCount(BeatCount[AHBWLOGBWPL-1:AHBWLOGBWPL-LLENLOGBWPL]),
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.FinalWriteData(LSUWriteDataM), .SelHPTW,
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.CacheStall(DCacheStallM), .CacheMiss(DCacheMiss), .CacheAccess(DCacheAccess),
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.CacheCommitted(DCacheCommittedM),
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.CacheBusAdr(DCacheBusAdr), .ReadDataWord(DCacheReadDataWordM),
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.FetchBuffer, .CacheBusRW,
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.CacheBusAck(DCacheBusAck), .InvalidateCache(1'b0));
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ahbcacheinterface #(.WORDSPERLINE(AHBWWORDSPERLINE), .LINELEN(LINELEN), .LOGWPL(AHBWLOGBWPL), .CACHE_ENABLED(`DCACHE)) ahbcacheinterface(
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ahbcacheinterface #(.BEATSPERLINE(BEATSPERLINE), .LINELEN(LINELEN), .LOGWPL(AHBWLOGBWPL), .CACHE_ENABLED(`DCACHE)) ahbcacheinterface(
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.HCLK(clk), .HRESETn(~reset), .Flush(FlushW),
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.HRDATA,
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.HSIZE(LSUHSIZE), .HBURST(LSUHBURST), .HTRANS(LSUHTRANS), .HWRITE(LSUHWRITE), .HREADY(LSUHREADY),
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.WordCount, .SelBusWord,
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.BeatCount, .SelBusBeat,
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.Funct3(LSUFunct3M), .HADDR(LSUHADDR), .CacheBusAdr(DCacheBusAdr), .CacheBusRW,
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.CacheBusAck(DCacheBusAck), .FetchBuffer, .PAdr(PAdrM),
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.Cacheable(CacheableOrFlushCacheM), .BusRW, .CPUBusy,
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@ -284,7 +284,7 @@ module lsu (
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for (index = 0; index < LLENPOVERAHBW; index++) begin:readdatalinesetsmux
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assign AHBWordSets[index] = DCacheReadDataWordM[(index*`AHBW)+`AHBW-1: (index*`AHBW)];
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end
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assign DCacheReadDataWordAHB = AHBWordSets[WordCount[$clog2(LLENPOVERAHBW)-1:0]];
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assign DCacheReadDataWordAHB = AHBWordSets[BeatCount[$clog2(LLENPOVERAHBW)-1:0]];
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end else assign DCacheReadDataWordAHB = DCacheReadDataWordM[`AHBW-1:0];
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mux2 #(`XLEN) LSUHWDATAMux(.d0(DCacheReadDataWordAHB), .d1(LSUWriteDataM[`AHBW-1:0]),
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.s(~(CacheableOrFlushCacheM)), .y(PreHWDATA));
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