forked from Github_Repos/cvw
Cleanup branch predictor files.
This commit is contained in:
Ross Thompson
parent
a14c71bd95
commit
d2e06d9ef0
@ -1,146 +0,0 @@
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///////////////////////////////////////////
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// gsharePredictor.sv
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//
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// Written: Shreya Sanghai
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// Email: ssanghai@hmc.edu
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// Created: March 16, 2021
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// Modified:
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//
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// Purpose: Global History Branch predictor with parameterized global history register
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//
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// A component of the CORE-V-WALLY configurable RISC-V project.
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//
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// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
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//
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// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
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//
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// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
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// except in compliance with the License, or, at your option, the Apache License version 2.0. You
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// may obtain a copy of the License at
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//
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// https://solderpad.org/licenses/SHL-2.1/
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//
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// Unless required by applicable law or agreed to in writing, any work distributed under the
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// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
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// either express or implied. See the License for the specific language governing permissions
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// and limitations under the License.
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////////////////////////////////////////////////////////////////////////////////////////////////
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`include "wally-config.vh"
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module foldedgshare #(parameter k = 16, depth = 10) (
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input logic clk,
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input logic reset,
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input logic StallF, StallD, StallE, StallM, StallW,
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input logic FlushD, FlushE, FlushM, FlushW,
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// input logic [`XLEN-1:0] LookUpPC,
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output logic [1:0] DirPredictionF,
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output logic DirPredictionWrongE,
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// update
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input logic [`XLEN-1:0] PCNextF, PCF, PCD, PCE, PCM,
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input logic BranchInstrF, BranchInstrD, BranchInstrE, BranchInstrM, BranchInstrW,
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input logic PCSrcE
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);
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logic MatchF, MatchD, MatchE, MatchM, MatchW;
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logic MatchNextX, MatchXF;
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logic [1:0] TableDirPredictionF, DirPredictionD, DirPredictionE;
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logic [1:0] NewDirPredictionF, NewDirPredictionD, NewDirPredictionE, NewDirPredictionM, NewDirPredictionW;
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logic [k-1:0] GHRF;
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logic [k:0] GHRD, OldGHRE, GHRE, GHRM, GHRW;
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logic [k-1:0] GHRNextF;
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logic [k:0] GHRNextD, GHRNextE, GHRNextM, GHRNextW;
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logic [k-1:0] IndexNextF, IndexF;
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logic [k-1:0] IndexD, IndexE, IndexM, IndexW;
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logic [depth-1:0] FinalIndexNextF, FinalIndexW;
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logic PCSrcM, PCSrcW;
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logic [`XLEN-1:0] PCW;
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logic [1:0] ForwardNewDirPrediction, ForwardDirPredictionF;
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localparam delta = 2 * depth - k;
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assign IndexNextF = GHRNextF ^ {PCNextF[k+1] ^ PCNextF[1], PCNextF[k:2]};
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assign IndexF = GHRF ^ {PCF[k+1] ^ PCF[1], PCF[k:2]};
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assign IndexD = GHRD[k-1:0] ^ {PCD[k+1] ^ PCD[1], PCD[k:2]};
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assign IndexE = GHRE[k-1:0] ^ {PCE[k+1] ^ PCE[1], PCE[k:2]};
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assign IndexM = GHRM[k-1:0] ^ {PCM[k+1] ^ PCM[1], PCM[k:2]};
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assign IndexW = GHRW[k-1:0] ^ {PCW[k+1] ^ PCW[1], PCW[k:2]};
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// just be dumb for now.
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//localparam int kToDepthRatio = (k+depth) / depth;
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assign FinalIndexNextF = IndexNextF[depth-1:0] ^ {{delta{1'b0}} , IndexNextF[k-1:depth]};
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assign FinalIndexW = IndexW[depth-1:0] ^ {{delta{1'b0}} , IndexW[k-1:depth]};
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ram2p1r1wbe #(2**depth, 2) PHT(.clk(clk),
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.ce1(~StallF | reset), .ce2(~StallW & ~FlushW),
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.ra1(FinalIndexNextF),
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.rd1(TableDirPredictionF),
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.wa2(FinalIndexW),
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.wd2(NewDirPredictionW),
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.we2(BranchInstrW & ~StallW & ~FlushW),
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.bwe2(1'b1));
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// if there are non-flushed branches in the pipeline we need to forward the prediction from that stage to the NextF demi stage
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// and then register for use in the Fetch stage.
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assign MatchF = BranchInstrF & ~FlushD & (IndexNextF == IndexF);
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assign MatchD = BranchInstrD & ~FlushE & (IndexNextF == IndexD);
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assign MatchE = BranchInstrE & ~FlushM & (IndexNextF == IndexE);
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assign MatchM = BranchInstrM & ~FlushW & (IndexNextF == IndexM);
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assign MatchW = BranchInstrW & (IndexNextF == IndexW);
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assign MatchNextX = MatchF | MatchD | MatchE | MatchM | MatchW;
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flopenr #(1) MatchReg(clk, reset, ~StallF, MatchNextX, MatchXF);
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assign ForwardNewDirPrediction = MatchF ? NewDirPredictionF :
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MatchD ? NewDirPredictionD :
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MatchE ? NewDirPredictionE :
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MatchM ? NewDirPredictionM :
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NewDirPredictionW;
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flopenr #(2) ForwardDirPredicitonReg(clk, reset, ~StallF, ForwardNewDirPrediction, ForwardDirPredictionF);
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assign DirPredictionF = MatchXF ? ForwardDirPredictionF : TableDirPredictionF;
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// DirPrediction pipeline
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flopenr #(2) PredictionRegD(clk, reset, ~StallD, DirPredictionF, DirPredictionD);
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flopenr #(2) PredictionRegE(clk, reset, ~StallE, DirPredictionD, DirPredictionE);
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// New prediction pipeline
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satCounter2 BPDirUpdateF(.BrDir(DirPredictionF[1]), .OldState(DirPredictionF), .NewState(NewDirPredictionF));
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flopenr #(2) NewPredDReg(clk, reset, ~StallD, NewDirPredictionF, NewDirPredictionD);
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satCounter2 BPDirUpdateE(.BrDir(PCSrcE), .OldState(DirPredictionE), .NewState(NewDirPredictionE));
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flopenr #(2) NewPredMReg(clk, reset, ~StallM, NewDirPredictionE, NewDirPredictionM);
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flopenr #(2) NewPredWReg(clk, reset, ~StallW, NewDirPredictionM, NewDirPredictionW);
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// PCSrc pipeline
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flopenrc #(1) PCSrcMReg(clk, reset, FlushM, ~StallM, PCSrcE, PCSrcM);
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flopenrc #(1) PCSrcWReg(clk, reset, FlushW, ~StallW, PCSrcM, PCSrcW);
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// GHR pipeline
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assign GHRNextF = FlushD ? GHRNextD[k:1] :
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BranchInstrF ? {DirPredictionF[1], GHRF[k-1:1]} :
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GHRF;
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flopenr #(k) GHRFReg(clk, reset, (~StallF) | FlushD, GHRNextF, GHRF);
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assign GHRNextD = FlushD ? GHRNextE : {DirPredictionF[1], GHRF};
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flopenr #(k+1) GHRDReg(clk, reset, (~StallD) | FlushD, GHRNextD, GHRD);
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assign GHRNextE = FlushE ? GHRNextM : GHRD;
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flopenr #(k+1) GHREReg(clk, reset, (~StallE) | FlushE, GHRNextE, OldGHRE);
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assign GHRE = BranchInstrE ? {PCSrcE, OldGHRE[k-1:0]} : OldGHRE;
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assign GHRNextM = FlushM ? GHRNextW : GHRE;
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flopenr #(k+1) GHRMReg(clk, reset, (~StallM) | FlushM, GHRNextM, GHRM);
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assign GHRNextW = FlushW ? GHRW : GHRM;
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flopenr #(k+1) GHRWReg(clk, reset, (BranchInstrM & ~StallW) | FlushW, GHRNextW, GHRW);
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assign DirPredictionWrongE = PCSrcE != DirPredictionE[1] & BranchInstrE;
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flopenr #(`XLEN) PCWReg(clk, reset, ~StallW, PCM, PCW);
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endmodule
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@ -1,80 +0,0 @@
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///////////////////////////////////////////
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// globalHistoryPredictor.sv
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//
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// Written: Shreya Sanghai
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// Email: ssanghai@hmc.edu
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// Created: March 16, 2021
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// Modified:
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//
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// Purpose: Global History Branch predictor with parameterized global history register
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//
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// A component of the CORE-V-WALLY configurable RISC-V project.
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//
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// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
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//
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// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
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//
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// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
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// except in compliance with the License, or, at your option, the Apache License version 2.0. You
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// may obtain a copy of the License at
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//
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// https://solderpad.org/licenses/SHL-2.1/
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//
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// Unless required by applicable law or agreed to in writing, any work distributed under the
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// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
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// either express or implied. See the License for the specific language governing permissions
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// and limitations under the License.
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////////////////////////////////////////////////////////////////////////////////////////////////
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`include "wally-config.vh"
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module globalhistory #(parameter k = 10) (
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input logic clk,
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input logic reset,
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input logic StallF, StallD, StallE, StallM, StallW,
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input logic FlushD, FlushE, FlushM, FlushW,
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output logic [1:0] DirPredictionF,
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output logic DirPredictionWrongE,
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// update
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input logic BranchInstrE, BranchInstrM, PCSrcE
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);
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logic [k-1:0] IndexNextF, IndexE;
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logic [1:0] DirPredictionD, DirPredictionE;
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logic [1:0] NewDirPredictionE, NewDirPredictionM;
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logic [k-1:0] GHRF, GHRD, GHRE, GHRM, GHR;
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logic [k-1:0] GHRNext;
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logic PCSrcM;
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assign IndexNextF = GHR;
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assign IndexE = GHRM;
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ram2p1r1wbe #(2**k, 2) PHT(.clk(clk),
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.ce1(~StallF), .ce2(~StallM & ~FlushM),
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.ra1(IndexNextF),
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.rd1(DirPredictionF),
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.wa2(IndexE),
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.wd2(NewDirPredictionM),
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.we2(BranchInstrM & ~StallW & ~FlushW),
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.bwe2(1'b1));
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flopenrc #(2) PredictionRegD(clk, reset, FlushD, ~StallD, DirPredictionF, DirPredictionD);
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flopenrc #(2) PredictionRegE(clk, reset, FlushE, ~StallE, DirPredictionD, DirPredictionE);
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satCounter2 BPDirUpdateE(.BrDir(PCSrcE), .OldState(DirPredictionE), .NewState(NewDirPredictionE));
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flopenrc #(2) NewPredictionRegM(clk, reset, FlushM, ~StallM, NewDirPredictionE, NewDirPredictionM);
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assign DirPredictionWrongE = PCSrcE != DirPredictionE[1] & BranchInstrE;
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assign GHRNext = BranchInstrM ? {PCSrcM, GHR[k-1:1]} : GHR;
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flopenr #(k) GHRReg(clk, reset, ~StallM & ~FlushM & BranchInstrM, GHRNext, GHR);
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flopenrc #(1) PCSrcMReg(clk, reset, FlushM, ~StallM, PCSrcE, PCSrcM);
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flopenrc #(k) GHRFReg(clk, reset, FlushD, ~StallF, GHR, GHRF);
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flopenrc #(k) GHRDReg(clk, reset, FlushD, ~StallD, GHRF, GHRD);
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flopenrc #(k) GHREReg(clk, reset, FlushE, ~StallE, GHRD, GHRE);
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flopenrc #(k) GHRMReg(clk, reset, FlushM, ~StallM, GHRE, GHRM);
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endmodule
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@ -1,12 +1,13 @@
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///////////////////////////////////////////
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// globalHistoryPredictor.sv
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// gshare.sv
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//
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// Written: Shreya Sanghai
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// Email: ssanghai@hmc.edu
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// Created: March 16, 2021
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// Modified:
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// Written: Ross Thompson
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// Email: ross1728@gmail.com
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// Created: 16 March 2021
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// Adapted from ssanghai@hmc.edu (Shreya Sanghai)
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// Modified: 20 February 2023
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//
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// Purpose: Global History Branch predictor with parameterized global history register
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// Purpose: gshare and Global History Branch predictors
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//
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// A component of the CORE-V-WALLY configurable RISC-V project.
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//
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@ -1,10 +1,11 @@
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///////////////////////////////////////////
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// globalHistoryPredictor.sv
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// gsharebasic.sv
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//
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// Written: Shreya Sanghai
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// Email: ssanghai@hmc.edu
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// Created: March 16, 2021
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// Modified:
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// Written: Ross Thompson
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// Email: ross1728@gmail.com
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// Created: 16 March 2021
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// Adapted from ssanghai@hmc.edu (Shreya Sanghai) global history predictor implementation.
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// Modified: 20 February 2023
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//
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// Purpose: Global History Branch predictor with parameterized global history register
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//
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@ -1,219 +0,0 @@
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///////////////////////////////////////////
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// gsharePredictor.sv
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//
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// Written: Shreya Sanghai
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// Email: ssanghai@hmc.edu
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// Created: March 16, 2021
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// Modified:
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//
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// Purpose: Global History Branch predictor with parameterized global history register
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//
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// A component of the Wally configurable RISC-V project.
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//
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// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
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//
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// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
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//
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// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
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// except in compliance with the License, or, at your option, the Apache License version 2.0. You
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// may obtain a copy of the License at
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//
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// https://solderpad.org/licenses/SHL-2.1/
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//
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// Unless required by applicable law or agreed to in writing, any work distributed under the
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// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
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// either express or implied. See the License for the specific language governing permissions
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// and limitations under the License.
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////////////////////////////////////////////////////////////////////////////////////////////////
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`include "wally-config.vh"
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module optgshare #(parameter k = 10) (
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input logic clk,
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input logic reset,
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input logic StallF, StallD, StallE, StallM, StallW,
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input logic FlushD, FlushE, FlushM, FlushW,
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// input logic [`XLEN-1:0] LookUpPC,
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output logic [1:0] DirPredictionF,
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output logic DirPredictionWrongE,
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// update
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input logic [`XLEN-1:0] PCNextF, PCF, PCD, PCE, PCM,
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input logic BranchInstrF, BranchInstrD, BranchInstrE, BranchInstrM, BranchInstrW,
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input logic PCSrcE
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);
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logic MatchF, MatchD, MatchE, MatchM, MatchW;
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logic MatchNextX, MatchXF;
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logic [1:0] TableDirPredictionF, DirPredictionD, DirPredictionE;
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logic [1:0] NewDirPredictionF, NewDirPredictionD, NewDirPredictionE, NewDirPredictionM, NewDirPredictionW;
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logic [k-1:0] GHRF;
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logic [k:0] GHRD, OldGHRE, GHRE, GHRM, GHRW;
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logic [k-1:0] GHRNextF;
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logic [k:0] GHRNextD, GHRNextE, GHRNextM, GHRNextW;
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logic [k-1:0] IndexNextF, IndexF;
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logic [k-1:0] IndexD, IndexE, IndexM, IndexW;
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logic PCSrcM, PCSrcW;
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logic [`XLEN-1:0] PCW;
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logic [1:0] ForwardNewDirPrediction, ForwardDirPredictionF;
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logic [k+4:0] GHRNext, GHR;
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logic GHRUpdateEn;
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assign GHRUpdateEn = BranchInstrF | (DirPredictionWrongE & BranchInstrE) |
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FlushD | FlushE | FlushM | FlushW;
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// it doesn't work this way. Instead we need to see how many branch instructions are flushed.
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// then shift over by that amount.
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logic RemoveBrW, RemoveBrM, RemoveBrE, RemoveBrD, RemoveBrF, RemoveBrNextF;
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assign RemoveBrW = '0;
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assign RemoveBrM = BranchInstrM & FlushW;
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assign RemoveBrE = BranchInstrE & FlushM;
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assign RemoveBrD = BranchInstrD & FlushE;
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assign RemoveBrF = BranchInstrF & FlushD;
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assign RemoveBrNextF = BranchInstrF & FlushD;
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always_comb begin
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casez ({BranchInstrF, DirPredictionWrongE, RemoveBrF, RemoveBrD, RemoveBrE, RemoveBrM})
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6'b00_0000: GHRNext = GHR; // no change
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6'b00_0001: GHRNext = {GHR[k+4:k+1], GHR[k-1:0], 1'b0}; // RemoveBrM
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6'b0?_0010: GHRNext = {GHR[k+4:k+2], GHR[k:0], 1'b0}; // RemoveBrE
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6'b0?_0011: GHRNext = {GHR[k+4:k+2], GHR[k-1:0], 2'b0}; // RemoveBrE, RemoveBrM
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6'b00_0100: GHRNext = {GHR[k+4:k+2], GHR[k-1:0], 2'b0}; // RemoveBrD
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6'b00_0101: GHRNext = {GHR[k+4:k+3], GHR[k+1:0], 1'b0}; // RemoveBrD, RemoveBrM
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6'b0?_0110: GHRNext = {GHR[k+4:k+3], GHR[k+1], GHR[k-1:0], 2'b0}; // RemoveBrD, RemoveBrE
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6'b0?_0111: GHRNext = {GHR[k+4:k+3], GHR[k-1:0], 3'b0}; // RemoveBrD, RemoveBrE, RemoveBrM
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6'b?0_1000: GHRNext = {GHR[k+2:0], 2'b0}; // RemoveBrF,
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6'b?0_1001: GHRNext = {GHR[k+2:k+1], GHR[k-1:0], 3'b0}; // RemoveBrF, RemoveBrM
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6'b??_1010: GHRNext = {GHR[k+2], GHR[k:0], 3'b0}; // RemoveBrF, RemoveBrE
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6'b??_1011: GHRNext = {GHR[k+2], GHR[k-1:0], 4'b0}; // RemoveBrF, RemoveBrE, RemoveBrM
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6'b?0_1100: GHRNext = {GHR[k+1:0], 3'b0}; // RemoveBrF, RemoveBrD
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6'b?0_1101: GHRNext = {GHR[k+1], GHR[k-1:0], 4'b0}; // RemoveBrF, RemoveBrD, RemoveBrM
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6'b??_1110: GHRNext = {GHR[k:0], 4'b0}; // RemoveBrF, RemoveBrD, RemoveBrE
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6'b??_1111: GHRNext = {GHR[k-1:0], 5'b0}; // RemoveBrF, RemoveBrD, RemoveBrE, RemoveBrM
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|
||||
6'b?1_0000: GHRNext = {PCSrcE, GHR[k+3:0]}; // Miss prediction, no branches to flushes
|
||||
6'b?1_0001: GHRNext = {PCSrcE, GHR[k+3:k], GHR[k-1:1], 1'b0}; // Miss prediction, branch in Memory stage dropped
|
||||
|
||||
6'b?1_1100: GHRNext = {PCSrcE, GHR[k+1:0], 2'b00}; // Miss prediction, cannot have RemoveBrE
|
||||
6'b?1_1101: GHRNext = {PCSrcE, GHR[k+1], GHR[k-1:0], 3'b0}; // Miss prediction, cannot have RemoveBrE
|
||||
6'b10_0000: GHRNext = {DirPredictionF[1], GHR[k+4:1]};
|
||||
6'b10_0001: GHRNext = {DirPredictionF[1], GHR[k+4:k+1], GHR[k-1:1], 1'b0};
|
||||
6'b10_0010: GHRNext = {DirPredictionF[1], GHR[k+4:k+2], GHR[k:1], 1'b0};
|
||||
6'b10_0011: GHRNext = {DirPredictionF[1], GHR[k+4:k+2], GHR[k-1:1], 2'b0};
|
||||
6'b10_0100: GHRNext = {DirPredictionF[1], GHR[k+4:k+3], GHR[k+1:1], 1'b0};
|
||||
6'b10_0101: GHRNext = {DirPredictionF[1], GHR[k+4:k+3], GHR[k+1], GHR[k-1:1], 2'b0};
|
||||
6'b10_0110: GHRNext = {DirPredictionF[1], GHR[k+4:k+3], GHR[k], GHR[k-1:1], 2'b0};
|
||||
6'b10_0111: GHRNext = {DirPredictionF[1], GHR[k+4:k+3], GHR[k-1:1], 3'b0};
|
||||
|
||||
default: GHRNext = GHR;
|
||||
endcase
|
||||
end
|
||||
|
||||
flopenr #(k+5) GHRReg(clk, reset, GHRUpdateEn, GHRNext, GHR);
|
||||
logic [k-1:0] GHRNextF_temp, GHRF_temp;
|
||||
logic [k:0] GHRD_temp, GHRE_temp, GHRM_temp, GHRW_temp;
|
||||
logic GHRFExtra_temp;
|
||||
|
||||
// these are also in the ieu controller. should create inputs.
|
||||
logic InstrValidF, InstrValidD, InstrValidE, InstrValidM, InstrValidW;
|
||||
flopenrc #(1) InstrValidFReg(clk, reset, FlushD, ~StallF, 1'b1, InstrValidF);
|
||||
flopenrc #(1) InstrValidDReg(clk, reset, FlushD, ~StallD, InstrValidF, InstrValidD);
|
||||
flopenrc #(1) InstrValidEReg(clk, reset, FlushE, ~StallE, InstrValidD, InstrValidE);
|
||||
flopenrc #(1) InstrValidMReg(clk, reset, FlushM, ~StallM, InstrValidE, InstrValidM);
|
||||
flopenrc #(1) InstrValidWReg(clk, reset, FlushW, ~StallW, InstrValidM, InstrValidW);
|
||||
|
||||
|
||||
assign GHRNextF_temp = GHRNext[k+4:5];
|
||||
assign GHRF_temp = InstrValidF ? GHR[k+3:4] : GHRNextF_temp;
|
||||
assign GHRFExtra_temp = InstrValidF ? 1'b0 : GHR[k+4];
|
||||
assign GHRD_temp = InstrValidD ? GHR[k+3:3] : {GHRFExtra_temp, GHRF_temp};
|
||||
assign GHRE_temp = InstrValidE ? GHR[k+2:2] : GHRD_temp;
|
||||
assign GHRM_temp = InstrValidM ? GHR[k+1:1] : GHRE_temp;
|
||||
assign GHRW_temp = InstrValidW ? GHR[k:0] : GHRM_temp;
|
||||
|
||||
|
||||
assign IndexNextF = GHRNextF ^ {PCNextF[k+1] ^ PCNextF[1], PCNextF[k:2]};
|
||||
assign IndexF = GHRF ^ {PCF[k+1] ^ PCF[1], PCF[k:2]};
|
||||
assign IndexD = GHRD[k-1:0] ^ {PCD[k+1] ^ PCD[1], PCD[k:2]};
|
||||
assign IndexE = GHRE[k-1:0] ^ {PCE[k+1] ^ PCE[1], PCE[k:2]};
|
||||
assign IndexM = GHRM[k-1:0] ^ {PCM[k+1] ^ PCM[1], PCM[k:2]};
|
||||
assign IndexW = GHRW[k-1:0] ^ {PCW[k+1] ^ PCW[1], PCW[k:2]};
|
||||
|
||||
ram2p1r1wbe #(2**k, 2) PHT(.clk(clk),
|
||||
.ce1(~StallF | reset), .ce2(~StallW & ~FlushW),
|
||||
.ra1(IndexNextF),
|
||||
.rd1(TableDirPredictionF),
|
||||
.wa2(IndexW),
|
||||
.wd2(NewDirPredictionW),
|
||||
.we2(BranchInstrW & ~StallW & ~FlushW),
|
||||
.bwe2(1'b1));
|
||||
|
||||
// if there are non-flushed branches in the pipeline we need to forward the prediction from that stage to the NextF demi stage
|
||||
// and then register for use in the Fetch stage.
|
||||
assign MatchF = BranchInstrF & ~FlushD & (IndexNextF == IndexF);
|
||||
assign MatchD = BranchInstrD & ~FlushE & (IndexNextF == IndexD);
|
||||
assign MatchE = BranchInstrE & ~FlushM & (IndexNextF == IndexE);
|
||||
assign MatchM = BranchInstrM & ~FlushW & (IndexNextF == IndexM);
|
||||
assign MatchW = BranchInstrW & (IndexNextF == IndexW);
|
||||
assign MatchNextX = MatchF | MatchD | MatchE | MatchM | MatchW;
|
||||
|
||||
flopenr #(1) MatchReg(clk, reset, ~StallF, MatchNextX, MatchXF);
|
||||
|
||||
assign ForwardNewDirPrediction = MatchF ? NewDirPredictionF :
|
||||
MatchD ? NewDirPredictionD :
|
||||
MatchE ? NewDirPredictionE :
|
||||
MatchM ? NewDirPredictionM :
|
||||
NewDirPredictionW;
|
||||
|
||||
flopenr #(2) ForwardDirPredicitonReg(clk, reset, ~StallF, ForwardNewDirPrediction, ForwardDirPredictionF);
|
||||
|
||||
assign DirPredictionF = MatchXF ? ForwardDirPredictionF : TableDirPredictionF;
|
||||
|
||||
// DirPrediction pipeline
|
||||
flopenr #(2) PredictionRegD(clk, reset, ~StallD, DirPredictionF, DirPredictionD);
|
||||
flopenr #(2) PredictionRegE(clk, reset, ~StallE, DirPredictionD, DirPredictionE);
|
||||
|
||||
// New prediction pipeline
|
||||
satCounter2 BPDirUpdateF(.BrDir(DirPredictionF[1]), .OldState(DirPredictionF), .NewState(NewDirPredictionF));
|
||||
flopenr #(2) NewPredDReg(clk, reset, ~StallD, NewDirPredictionF, NewDirPredictionD);
|
||||
satCounter2 BPDirUpdateE(.BrDir(PCSrcE), .OldState(DirPredictionE), .NewState(NewDirPredictionE));
|
||||
flopenr #(2) NewPredMReg(clk, reset, ~StallM, NewDirPredictionE, NewDirPredictionM);
|
||||
flopenr #(2) NewPredWReg(clk, reset, ~StallW, NewDirPredictionM, NewDirPredictionW);
|
||||
|
||||
// PCSrc pipeline
|
||||
flopenrc #(1) PCSrcMReg(clk, reset, FlushM, ~StallM, PCSrcE, PCSrcM);
|
||||
flopenrc #(1) PCSrcWReg(clk, reset, FlushW, ~StallW, PCSrcM, PCSrcW);
|
||||
|
||||
// GHR pipeline
|
||||
assign GHRNextF = FlushD ? GHRNextD[k:1] :
|
||||
BranchInstrF ? {DirPredictionF[1], GHRF[k-1:1]} :
|
||||
GHRF;
|
||||
|
||||
flopenr #(k) GHRFReg(clk, reset, (~StallF) | FlushD, GHRNextF, GHRF);
|
||||
|
||||
assign GHRNextD = FlushD ? GHRNextE : {DirPredictionF[1], GHRF};
|
||||
flopenr #(k+1) GHRDReg(clk, reset, (~StallD) | FlushD, GHRNextD, GHRD);
|
||||
|
||||
assign GHRNextE = FlushE ? GHRNextM : GHRD;
|
||||
flopenr #(k+1) GHREReg(clk, reset, (~StallE) | FlushE, GHRNextE, OldGHRE);
|
||||
assign GHRE = BranchInstrE ? {PCSrcE, OldGHRE[k-1:0]} : OldGHRE;
|
||||
|
||||
assign GHRNextM = FlushM ? GHRNextW : GHRE;
|
||||
flopenr #(k+1) GHRMReg(clk, reset, (~StallM) | FlushM, GHRNextM, GHRM);
|
||||
|
||||
assign GHRNextW = FlushW ? GHRW : GHRM;
|
||||
flopenr #(k+1) GHRWReg(clk, reset, (BranchInstrM & ~StallW) | FlushW, GHRNextW, GHRW);
|
||||
|
||||
assign DirPredictionWrongE = PCSrcE != DirPredictionE[1] & BranchInstrE;
|
||||
|
||||
flopenr #(`XLEN) PCWReg(clk, reset, ~StallW, PCM, PCW);
|
||||
|
||||
endmodule
|
||||
@ -1,136 +0,0 @@
|
||||
///////////////////////////////////////////
|
||||
// speculativeglobalhistory.sv
|
||||
//
|
||||
// Written: Shreya Sanghai
|
||||
// Email: ssanghai@hmc.edu
|
||||
// Created: March 16, 2021
|
||||
// Modified:
|
||||
//
|
||||
// Purpose: Global History Branch predictor with parameterized global history register
|
||||
//
|
||||
// A component of the CORE-V-WALLY configurable RISC-V project.
|
||||
//
|
||||
// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
|
||||
//
|
||||
// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
|
||||
//
|
||||
// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
|
||||
// except in compliance with the License, or, at your option, the Apache License version 2.0. You
|
||||
// may obtain a copy of the License at
|
||||
//
|
||||
// https://solderpad.org/licenses/SHL-2.1/
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, any work distributed under the
|
||||
// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
|
||||
// either express or implied. See the License for the specific language governing permissions
|
||||
// and limitations under the License.
|
||||
////////////////////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
`include "wally-config.vh"
|
||||
|
||||
module speculativeglobalhistory #(parameter int k = 10 ) (
|
||||
input logic clk,
|
||||
input logic reset,
|
||||
input logic StallF, StallD, StallE, StallM, StallW,
|
||||
input logic FlushD, FlushE, FlushM, FlushW,
|
||||
output logic [1:0] DirPredictionF,
|
||||
output logic DirPredictionWrongE,
|
||||
// update
|
||||
input logic [3:0] PredInstrClassF,
|
||||
input logic [3:0] InstrClassD, InstrClassE, InstrClassM,
|
||||
input logic [3:0] WrongPredInstrClassD,
|
||||
input logic PCSrcE
|
||||
);
|
||||
|
||||
logic MatchF, MatchD, MatchE;
|
||||
logic MatchNextX, MatchXF;
|
||||
|
||||
logic [1:0] TableDirPredictionF, DirPredictionD, DirPredictionE;
|
||||
logic [1:0] NewDirPredictionE;
|
||||
|
||||
logic [k-1:0] GHRF, GHRD, GHRE, GHRM;
|
||||
logic GHRLastF;
|
||||
logic [k-1:0] GHRNextF, GHRNextD, GHRNextE, GHRNextM;
|
||||
logic [k-1:0] IndexNextF, IndexF, IndexD, IndexE;
|
||||
logic [1:0] ForwardNewDirPrediction, ForwardDirPredictionF;
|
||||
|
||||
logic FlushDOrDirWrong;
|
||||
|
||||
assign IndexNextF = GHRNextF;
|
||||
assign IndexF = GHRF ;
|
||||
assign IndexD = GHRD[k-1:0] ;
|
||||
assign IndexE = GHRE[k-1:0] ;
|
||||
|
||||
ram2p1r1wbe #(2**k, 2) PHT(.clk(clk),
|
||||
.ce1(~StallF | reset), .ce2(~StallM & ~FlushM),
|
||||
.ra1(IndexNextF),
|
||||
.rd1(TableDirPredictionF),
|
||||
.wa2(IndexE),
|
||||
.wd2(NewDirPredictionE),
|
||||
.we2(InstrClassE[0]),
|
||||
.bwe2(1'b1));
|
||||
|
||||
// if there are non-flushed branches in the pipeline we need to forward the prediction from that stage to the NextF demi stage
|
||||
// and then register for use in the Fetch stage.
|
||||
assign MatchF = PredInstrClassF[0] & ~FlushD & (IndexNextF == IndexF);
|
||||
assign MatchD = InstrClassD[0] & ~FlushE & (IndexNextF == IndexD);
|
||||
assign MatchE = InstrClassE[0] & ~FlushM & (IndexNextF == IndexE);
|
||||
assign MatchNextX = MatchF | MatchD | MatchE;
|
||||
|
||||
flopenr #(1) MatchReg(clk, reset, ~StallF, MatchNextX, MatchXF);
|
||||
|
||||
assign ForwardNewDirPrediction = MatchF ? {2{DirPredictionF[1]}} :
|
||||
MatchD ? {2{DirPredictionD[1]}} :
|
||||
NewDirPredictionE ;
|
||||
|
||||
flopenr #(2) ForwardDirPredicitonReg(clk, reset, ~StallF, ForwardNewDirPrediction, ForwardDirPredictionF);
|
||||
|
||||
assign DirPredictionF = MatchXF ? ForwardDirPredictionF : TableDirPredictionF;
|
||||
|
||||
// DirPrediction pipeline
|
||||
flopenr #(2) PredictionRegD(clk, reset, ~StallD, DirPredictionF, DirPredictionD);
|
||||
flopenr #(2) PredictionRegE(clk, reset, ~StallE, DirPredictionD, DirPredictionE);
|
||||
|
||||
|
||||
satCounter2 BPDirUpdateE(.BrDir(PCSrcE), .OldState(DirPredictionE), .NewState(NewDirPredictionE));
|
||||
|
||||
// GHR pipeline
|
||||
|
||||
// If Fetch has a branch, speculatively insert prediction into the GHR
|
||||
// If the front end is flushed or the direction prediction is wrong, reset to
|
||||
// most recent valid GHR. For a BP wrong this is GHRD with the correct prediction shifted in.
|
||||
// For FlushE this is GHRE. GHRNextE is both.
|
||||
logic [k-1:0] GHRClassWrongAndPredF;
|
||||
logic [k-1:0] GHRClassWrong;
|
||||
mux2 #(k) GHRClassWrongAndPredFMux({DirPredictionF[1], DirPredictionD[1], GHRF[k-1:2]}, {DirPredictionF[1], GHRF[k-2:0]}, ~InstrClassD[0], GHRClassWrongAndPredF);
|
||||
|
||||
assign FlushDOrDirWrong = FlushD | DirPredictionWrongE;
|
||||
// mux3 #(k) GHRFMux(GHRF, {DirPredictionF[1], GHRF[k-1:1]}, GHRNextE[k-1:0],
|
||||
// {FlushDOrDirWrong, PredInstrClassF[0]}, GHRNextF);
|
||||
|
||||
mux5 #(k) GHRFMux(GHRF, {DirPredictionF[1], GHRF[k-1:1]}, GHRClassWrong, GHRClassWrongAndPredF, GHRNextE[k-1:0],
|
||||
{FlushDOrDirWrong, WrongPredInstrClassD[0], PredInstrClassF[0]}, GHRNextF);
|
||||
|
||||
// Need 1 extra bit to store the shifted out GHRF if repair needs to back shift.
|
||||
flopenr #(k) GHRFReg(clk, reset, ~StallF | FlushDOrDirWrong, GHRNextF, GHRF);
|
||||
flopenr #(1) GHRFLastReg(clk, reset, ~StallF | FlushDOrDirWrong, GHRF[0], GHRLastF);
|
||||
|
||||
// With instruction class prediction, the class could be wrong and is checked in Decode.
|
||||
// If it is wrong and branch does exist then shift right and insert the prediction.
|
||||
// If the branch does not exist then shift left and use GHRLastF to restore the LSB.
|
||||
mux2 #(k) GHRClassWrongMux({DirPredictionD[1], GHRF[k-1:1]}, {GHRF[k-2:0], GHRLastF}, ~InstrClassD[0], GHRClassWrong);
|
||||
// As with GHRF FlushD and wrong direction prediction flushes the pipeline and restores to GHRNextE.
|
||||
mux3 #(k) GHRDMux(GHRF, GHRClassWrong, GHRNextE, {FlushDOrDirWrong, WrongPredInstrClassD[0]}, GHRNextD);
|
||||
|
||||
flopenr #(k) GHRDReg(clk, reset, ~StallD | FlushDOrDirWrong, GHRNextD, GHRD);
|
||||
|
||||
mux3 #(k) GHREMux(GHRD, GHRNextM, {PCSrcE, GHRD[k-2:0]}, {InstrClassE[0] & ~FlushM, FlushE}, GHRNextE);
|
||||
|
||||
flopenr #(k) GHREReg(clk, reset, (~StallE) | FlushE, GHRNextE, GHRE);
|
||||
|
||||
assign GHRNextM = FlushM ? GHRM : GHRE;
|
||||
flopenr #(k) GHRMReg(clk, reset, (InstrClassM[0] & ~StallM) | FlushM, GHRNextM, GHRM);
|
||||
|
||||
assign DirPredictionWrongE = PCSrcE != DirPredictionE[1] & InstrClassE[0];
|
||||
|
||||
endmodule
|
||||
@ -1,137 +0,0 @@
|
||||
///////////////////////////////////////////
|
||||
// gsharePredictor.sv
|
||||
//
|
||||
// Written: Shreya Sanghai
|
||||
// Email: ssanghai@hmc.edu
|
||||
// Created: March 16, 2021
|
||||
// Modified:
|
||||
//
|
||||
// Purpose: Global History Branch predictor with parameterized global history register
|
||||
//
|
||||
// A component of the CORE-V-WALLY configurable RISC-V project.
|
||||
//
|
||||
// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
|
||||
//
|
||||
// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
|
||||
//
|
||||
// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
|
||||
// except in compliance with the License, or, at your option, the Apache License version 2.0. You
|
||||
// may obtain a copy of the License at
|
||||
//
|
||||
// https://solderpad.org/licenses/SHL-2.1/
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, any work distributed under the
|
||||
// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
|
||||
// either express or implied. See the License for the specific language governing permissions
|
||||
// and limitations under the License.
|
||||
////////////////////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
`include "wally-config.vh"
|
||||
|
||||
module speculativegshare #(parameter int k = 10 ) (
|
||||
input logic clk,
|
||||
input logic reset,
|
||||
input logic StallF, StallD, StallE, StallM, StallW,
|
||||
input logic FlushD, FlushE, FlushM, FlushW,
|
||||
output logic [1:0] DirPredictionF,
|
||||
output logic DirPredictionWrongE,
|
||||
// update
|
||||
input logic [`XLEN-1:0] PCNextF, PCF, PCD, PCE,
|
||||
input logic [3:0] PredInstrClassF,
|
||||
input logic [3:0] InstrClassD, InstrClassE, InstrClassM,
|
||||
input logic [3:0] WrongPredInstrClassD,
|
||||
input logic PCSrcE
|
||||
);
|
||||
|
||||
logic MatchF, MatchD, MatchE;
|
||||
logic MatchNextX, MatchXF;
|
||||
|
||||
logic [1:0] TableDirPredictionF, DirPredictionD, DirPredictionE;
|
||||
logic [1:0] NewDirPredictionE;
|
||||
|
||||
logic [k-1:0] GHRF, GHRD, GHRE, GHRM;
|
||||
logic GHRLastF;
|
||||
logic [k-1:0] GHRNextF, GHRNextD, GHRNextE, GHRNextM;
|
||||
logic [k-1:0] IndexNextF, IndexF, IndexD, IndexE;
|
||||
logic [1:0] ForwardNewDirPrediction, ForwardDirPredictionF;
|
||||
|
||||
logic FlushDOrDirWrong;
|
||||
|
||||
assign IndexNextF = GHRNextF ^ {PCNextF[k+1] ^ PCNextF[1], PCNextF[k:2]};
|
||||
assign IndexF = GHRF ^ {PCF[k+1] ^ PCF[1], PCF[k:2]};
|
||||
assign IndexD = GHRD[k-1:0] ^ {PCD[k+1] ^ PCD[1], PCD[k:2]};
|
||||
assign IndexE = GHRE[k-1:0] ^ {PCE[k+1] ^ PCE[1], PCE[k:2]};
|
||||
|
||||
ram2p1r1wbe #(2**k, 2) PHT(.clk(clk),
|
||||
.ce1(~StallF | reset), .ce2(~StallM & ~FlushM),
|
||||
.ra1(IndexNextF),
|
||||
.rd1(TableDirPredictionF),
|
||||
.wa2(IndexE),
|
||||
.wd2(NewDirPredictionE),
|
||||
.we2(InstrClassE[0]),
|
||||
.bwe2(1'b1));
|
||||
|
||||
// if there are non-flushed branches in the pipeline we need to forward the prediction from that stage to the NextF demi stage
|
||||
// and then register for use in the Fetch stage.
|
||||
assign MatchF = PredInstrClassF[0] & ~FlushD & (IndexNextF == IndexF);
|
||||
assign MatchD = InstrClassD[0] & ~FlushE & (IndexNextF == IndexD);
|
||||
assign MatchE = InstrClassE[0] & ~FlushM & (IndexNextF == IndexE);
|
||||
assign MatchNextX = MatchF | MatchD | MatchE;
|
||||
|
||||
flopenr #(1) MatchReg(clk, reset, ~StallF, MatchNextX, MatchXF);
|
||||
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assign ForwardNewDirPrediction = MatchF ? {2{DirPredictionF[1]}} :
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MatchD ? {2{DirPredictionD[1]}} :
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NewDirPredictionE ;
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flopenr #(2) ForwardDirPredicitonReg(clk, reset, ~StallF, ForwardNewDirPrediction, ForwardDirPredictionF);
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||||
|
||||
assign DirPredictionF = MatchXF ? ForwardDirPredictionF : TableDirPredictionF;
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||||
|
||||
// DirPrediction pipeline
|
||||
flopenr #(2) PredictionRegD(clk, reset, ~StallD, DirPredictionF, DirPredictionD);
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||||
flopenr #(2) PredictionRegE(clk, reset, ~StallE, DirPredictionD, DirPredictionE);
|
||||
|
||||
|
||||
satCounter2 BPDirUpdateE(.BrDir(PCSrcE), .OldState(DirPredictionE), .NewState(NewDirPredictionE));
|
||||
|
||||
// GHR pipeline
|
||||
|
||||
// If Fetch has a branch, speculatively insert prediction into the GHR
|
||||
// If the front end is flushed or the direction prediction is wrong, reset to
|
||||
// most recent valid GHR. For a BP wrong this is GHRD with the correct prediction shifted in.
|
||||
// For FlushE this is GHRE. GHRNextE is both.
|
||||
logic [k-1:0] GHRClassWrongAndPredF;
|
||||
logic [k-1:0] GHRClassWrong;
|
||||
mux2 #(k) GHRClassWrongAndPredFMux({DirPredictionF[1], DirPredictionD[1], GHRF[k-1:2]}, {DirPredictionF[1], GHRF[k-2:0]}, ~InstrClassD[0], GHRClassWrongAndPredF);
|
||||
|
||||
assign FlushDOrDirWrong = FlushD | DirPredictionWrongE;
|
||||
// mux3 #(k) GHRFMux(GHRF, {DirPredictionF[1], GHRF[k-1:1]}, GHRNextE[k-1:0],
|
||||
// {FlushDOrDirWrong, PredInstrClassF[0]}, GHRNextF);
|
||||
|
||||
mux5 #(k) GHRFMux(GHRF, {DirPredictionF[1], GHRF[k-1:1]}, GHRClassWrong, GHRClassWrongAndPredF, GHRNextE[k-1:0],
|
||||
{FlushDOrDirWrong, WrongPredInstrClassD[0], PredInstrClassF[0]}, GHRNextF);
|
||||
|
||||
// Need 1 extra bit to store the shifted out GHRF if repair needs to back shift.
|
||||
flopenr #(k) GHRFReg(clk, reset, ~StallF | FlushDOrDirWrong, GHRNextF, GHRF);
|
||||
flopenr #(1) GHRFLastReg(clk, reset, ~StallF | FlushDOrDirWrong, GHRF[0], GHRLastF);
|
||||
|
||||
// With instruction class prediction, the class could be wrong and is checked in Decode.
|
||||
// If it is wrong and branch does exist then shift right and insert the prediction.
|
||||
// If the branch does not exist then shift left and use GHRLastF to restore the LSB.
|
||||
mux2 #(k) GHRClassWrongMux({DirPredictionD[1], GHRF[k-1:1]}, {GHRF[k-2:0], GHRLastF}, ~InstrClassD[0], GHRClassWrong);
|
||||
// As with GHRF FlushD and wrong direction prediction flushes the pipeline and restores to GHRNextE.
|
||||
mux3 #(k) GHRDMux(GHRF, GHRClassWrong, GHRNextE, {FlushDOrDirWrong, WrongPredInstrClassD[0]}, GHRNextD);
|
||||
|
||||
flopenr #(k) GHRDReg(clk, reset, ~StallD | FlushDOrDirWrong, GHRNextD, GHRD);
|
||||
|
||||
mux3 #(k) GHREMux(GHRD, GHRNextM, {PCSrcE, GHRD[k-2:0]}, {InstrClassE[0] & ~FlushM, FlushE}, GHRNextE);
|
||||
|
||||
flopenr #(k) GHREReg(clk, reset, (~StallE) | FlushE, GHRNextE, GHRE);
|
||||
|
||||
assign GHRNextM = FlushM ? GHRM : GHRE;
|
||||
flopenr #(k) GHRMReg(clk, reset, (InstrClassM[0] & ~StallM) | FlushM, GHRNextM, GHRM);
|
||||
|
||||
assign DirPredictionWrongE = PCSrcE != DirPredictionE[1] & InstrClassE[0];
|
||||
|
||||
endmodule
|
||||
Loading…
Reference in New Issue
Block a user