forked from Github_Repos/cvw
Finished FPU-LSU interface cleanup
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@ -44,8 +44,7 @@ module fpu (
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output logic FpLoadStoreM, // Fp load instruction? (to LSU)
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output logic FStallD, // Stall the decode stage (To HZU)
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output logic FWriteIntE, // integer register write enable (to IEU)
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output logic [`XLEN-1:0] FWriteDataE, // Data to be written to memory (to IEU) - only used if `XLEN >`FLEN *** delete this
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output logic [`FLEN-1:0] FWriteDataM, // Data to be written to memory (to IEU) - only used if `XLEN <`FLEN
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output logic [`FLEN-1:0] FWriteDataM, // Data to be written to memory (to LSU)
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output logic [`XLEN-1:0] FIntResM, // data to be written to integer register (to IEU)
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output logic [`XLEN-1:0] FCvtIntResW, // convert result to to be written to integer register (to IEU)
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output logic [1:0] FResSelW, // final result selection (to IEU)
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@ -59,6 +58,9 @@ module fpu (
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// - if there are any unsused bits the most significant bits are filled with 1s
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// single stored in a double: | 32 1s | single precision value |
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// - sets the underflow after rounding
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// LSU interface
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logic [`FLEN-1:0] FWriteDataE;
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// control signals
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logic FRegWriteW; // FP register write enable
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@ -289,18 +291,17 @@ module fpu (
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// - FP uses NaN-blocking format
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// - if there are any unsused bits the most significant bits are filled with 1s
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logic [`FLEN-1:0] WriteDataE;
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if(`FPSIZES == 1) assign WriteDataE = YE;
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else if(`FPSIZES == 2) assign WriteDataE = FmtE ? YE : {`FLEN/`LEN1{YE[`LEN1-1:0]}};
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if(`FPSIZES == 1) assign FWriteDataE = YE;
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else if(`FPSIZES == 2) assign FWriteDataE = FmtE ? YE : {`FLEN/`LEN1{YE[`LEN1-1:0]}};
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else
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always_comb
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case(FmtE)
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`Q_FMT: WriteDataE = YE;
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`D_FMT: WriteDataE = {`FLEN/`D_LEN{YE[`D_LEN-1:0]}};
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`S_FMT: WriteDataE = {`FLEN/`S_LEN{YE[`S_LEN-1:0]}};
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`H_FMT: WriteDataE = {`FLEN/`H_LEN{YE[`H_LEN-1:0]}};
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`Q_FMT: FWriteDataE = YE;
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`D_FMT: FWriteDataE = {`FLEN/`D_LEN{YE[`D_LEN-1:0]}};
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`S_FMT: FWriteDataE = {`FLEN/`S_LEN{YE[`S_LEN-1:0]}};
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`H_FMT: FWriteDataE = {`FLEN/`H_LEN{YE[`H_LEN-1:0]}};
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endcase
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flopenrc #(`FLEN) EMWriteDataReg (clk, reset, FlushM, ~StallM, WriteDataE, FWriteDataM);
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flopenrc #(`FLEN) FWriteDataMReg (clk, reset, FlushM, ~StallM, FWriteDataE, FWriteDataM);
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// NaN Block SrcA
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generate
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@ -45,7 +45,6 @@ module datapath (
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input logic JumpE,
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input logic BranchSignedE,
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input logic IllegalFPUInstrE,
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input logic [`XLEN-1:0] FWriteDataE,
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input logic [`XLEN-1:0] PCE,
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input logic [`XLEN-1:0] PCLinkE,
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output logic [1:0] FlagsE,
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@ -56,7 +55,7 @@ module datapath (
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input logic FWriteIntM,
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input logic [`XLEN-1:0] FIntResM,
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output logic [`XLEN-1:0] SrcAM,
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output logic [`XLEN-1:0] WriteDataE,
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output logic [`XLEN-1:0] WriteDataM,
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// Writeback stage signals
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input logic StallW, FlushW,
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(* mark_debug = "true" *) input logic RegWriteW,
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@ -118,6 +117,7 @@ module datapath (
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flopenrc #(`XLEN) SrcAMReg(clk, reset, FlushM, ~StallM, SrcAE, SrcAM);
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flopenrc #(`XLEN) IEUResultMReg(clk, reset, FlushM, ~StallM, IEUResultE, IEUResultM);
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flopenrc #(5) RdMReg(clk, reset, FlushM, ~StallM, RdE, RdM);
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flopenrc #(`XLEN) WriteDataMReg(clk, reset, FlushM, ~StallM, ForwardedSrcBE, WriteDataM);
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// Writeback stage pipeline register and logic
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flopenrc #(`XLEN) IFResultWReg(clk, reset, FlushW, ~StallW, IFResultM, IFResultW);
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@ -133,7 +133,6 @@ module datapath (
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assign IFResultM = IEUResultM;
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mux5 #(`XLEN) resultmuxW(IFResultW, ReadDataW, CSRReadValW, MDUResultW, SCResultW, ResultSrcW, ResultW);
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end
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assign WriteDataE = ForwardedSrcBE;
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// handle Store Conditional result if atomic extension supported
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if (`A_SUPPORTED) assign SCResultW = {{(`XLEN-1){1'b0}}, SquashSCW};
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@ -41,7 +41,6 @@ module ieu (
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input logic [`XLEN-1:0] PCLinkE,
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input logic FWriteIntE,
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input logic IllegalFPUInstrE,
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input logic [`XLEN-1:0] FWriteDataE,
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output logic [`XLEN-1:0] IEUAdrE,
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output logic MDUE, W64E,
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output logic [2:0] Funct3E,
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@ -51,7 +50,7 @@ module ieu (
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input logic SquashSCW, // from LSU
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output logic [1:0] MemRWM, // read/write control goes to LSU
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output logic [1:0] AtomicM, // atomic control goes to LSU
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output logic [`XLEN-1:0] WriteDataE, // Address and write data to LSU
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output logic [`XLEN-1:0] WriteDataM, // write data to LSU
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output logic [2:0] Funct3M, // size and signedness to LSU
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output logic [`XLEN-1:0] SrcAM, // to privilege and fpu
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@ -107,8 +106,8 @@ module ieu (
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datapath dp(
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.clk, .reset, .ImmSrcD, .InstrD, .StallE, .FlushE, .ForwardAE, .ForwardBE,
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.ALUControlE, .Funct3E, .ALUSrcAE, .ALUSrcBE, .ALUResultSrcE, .JumpE, .BranchSignedE, .IllegalFPUInstrE,
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.FWriteDataE, .PCE, .PCLinkE, .FlagsE, .IEUAdrE, .ForwardedSrcAE, .ForwardedSrcBE,
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.StallM, .FlushM, .FWriteIntM, .FIntResM, .SrcAM, .WriteDataE, .FResSelW,
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.PCE, .PCLinkE, .FlagsE, .IEUAdrE, .ForwardedSrcAE, .ForwardedSrcBE,
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.StallM, .FlushM, .FWriteIntM, .FIntResM, .SrcAM, .WriteDataM, .FResSelW,
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.StallW, .FlushW, .RegWriteW, .SquashSCW, .ResultSrcW, .ReadDataW, .FCvtIntResW,
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.CSRReadValW, .MDUResultW, .Rs1D, .Rs2D, .Rs1E, .Rs2E, .RdE, .RdM, .RdW);
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@ -50,7 +50,7 @@ module lsu (
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// address and write data
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input logic [`XLEN-1:0] IEUAdrE,
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(* mark_debug = "true" *)output logic [`XLEN-1:0] IEUAdrM,
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input logic [`XLEN-1:0] WriteDataE,
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(* mark_debug = "true" *)input logic [`XLEN-1:0] WriteDataM,
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output logic [`LLEN-1:0] ReadDataW,
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// cpu privilege
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input logic [1:0] PrivilegeModeW,
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@ -111,14 +111,12 @@ module lsu (
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logic SelLSUBusWord;
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logic DataDAPageFaultM;
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logic [`XLEN-1:0] LSUWriteDataM;
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logic [`XLEN-1:0] WriteDataM;
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logic [`LLEN-1:0] ReadDataM;
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logic [(`LLEN-1)/8:0] ByteMaskM, FinalByteMaskM;
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// *** TO DO: Burst mode
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flopenrc #(`XLEN) AddressMReg(clk, reset, FlushM, ~StallM, IEUAdrE, IEUAdrM);
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flopenrc #(`XLEN) WriteDataMReg(clk, reset, FlushM, ~StallM, WriteDataE, WriteDataM); // *** move this flop to IEU
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assign IEUAdrExtM = {2'b00, IEUAdrM};
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assign LSUStallM = DCacheStallM | InterlockStall | BusStall;
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