forked from Github_Repos/cvw
Oups found a bug with the new flush cache states.
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41c636ecfa
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731fbfc851
@ -260,15 +260,13 @@ add wave -noupdate -expand -group lsu -expand -group dcache -group {replacement
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add wave -noupdate -expand -group lsu -expand -group dcache -group {replacement policy} -expand -group DETAILS /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/WayExpanded
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add wave -noupdate -expand -group lsu -expand -group dcache -expand -group flush /testbench/dut/core/lsu/bus/dcache/dcache/LineDirty
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add wave -noupdate -expand -group lsu -expand -group dcache -expand -group flush /testbench/dut/core/lsu/bus/dcache/dcache/FlushWay
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add wave -noupdate -expand -group lsu -expand -group dcache -expand -group flush /testbench/dut/core/lsu/bus/dcache/dcache/RawFlushAdr
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add wave -noupdate -expand -group lsu -expand -group dcache -expand -group flush /testbench/dut/core/lsu/bus/dcache/dcache/OldFlushAdr
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add wave -noupdate -expand -group lsu -expand -group dcache -expand -group flush /testbench/dut/core/lsu/bus/dcache/dcache/NextFlushAdr
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add wave -noupdate -expand -group lsu -expand -group dcache -expand -group flush -radix hexadecimal /testbench/dut/core/lsu/bus/dcache/dcache/FlushAdr
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add wave -noupdate -expand -group lsu -expand -group dcache -expand -group flush /testbench/dut/core/lsu/bus/dcache/dcache/cachefsm/FlushWayFlag
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add wave -noupdate -expand -group lsu -expand -group dcache -expand -group flush /testbench/dut/core/lsu/bus/dcache/dcache/FlushWayCntEn
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add wave -noupdate -expand -group lsu -expand -group dcache -expand -group flush /testbench/dut/core/lsu/bus/dcache/dcache/cachefsm/FlushAdrCntEn
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add wave -noupdate -expand -group lsu -expand -group dcache -expand -group flush /testbench/dut/core/lsu/bus/dcache/dcache/FlushWayCntRst
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add wave -noupdate -expand -group lsu -expand -group dcache -expand -group flush /testbench/dut/core/lsu/bus/dcache/dcache/FlushAdrFlag
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add wave -noupdate -expand -group lsu -expand -group dcache -expand -group flush /testbench/dut/core/lsu/bus/dcache/dcache/cachefsm/SelFlush
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add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} /testbench/dut/core/lsu/bus/dcache/dcache/ClearDirty
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add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/SelectedWriteWordEn}
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add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/SetValidWay}
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@ -601,7 +599,7 @@ add wave -noupdate /testbench/dut/core/lsu/bus/dcache/dcache/FlushWay
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add wave -noupdate /testbench/dut/core/lsu/bus/dcache/dcache/cachefsm/FlushAdrCntEn
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add wave -noupdate /testbench/dut/core/lsu/bus/dcache/dcache/cachefsm/FlushWayCntEn
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TreeUpdate [SetDefaultTree]
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WaveRestoreCursors {{Cursor 2} {314596 ns} 1} {{Cursor 3} {314460 ns} 1} {{Cursor 4} {408937 ns} 0} {{Cursor 4} {329828 ns} 1} {{Cursor 5} {408936 ns} 1}
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WaveRestoreCursors {{Cursor 2} {314596 ns} 1} {{Cursor 3} {314460 ns} 1} {{Cursor 4} {329696 ns} 0} {{Cursor 4} {329828 ns} 1} {{Cursor 5} {408936 ns} 1}
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quietly wave cursor active 3
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configure wave -namecolwidth 250
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configure wave -valuecolwidth 314
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@ -617,4 +615,4 @@ configure wave -griddelta 40
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configure wave -timeline 0
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configure wave -timelineunits ns
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update
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WaveRestoreZoom {408747 ns} {409125 ns}
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WaveRestoreZoom {329508 ns} {329874 ns}
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33
pipelined/src/cache/cachefsm.sv
vendored
33
pipelined/src/cache/cachefsm.sv
vendored
@ -77,7 +77,7 @@ module cachefsm
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logic AMO, StoreAMO;
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logic AnyUpdateHit, AnyHit;
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logic AnyMiss;
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logic FlushFlag, FlushWayAndNotAdrFlag;
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logic FlushFlag;
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typedef enum logic [3:0] {STATE_READY, // hit states
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// miss states
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@ -87,8 +87,6 @@ module cachefsm
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STATE_MISS_READ_DELAY, // required for back to back reads. structural hazard on writting SRAM
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// flush cache
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STATE_FLUSH,
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STATE_FLUSH_CHECK,
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STATE_FLUSH_INCR,
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STATE_FLUSH_WRITE_BACK} statetype;
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(* mark_debug = "true" *) statetype CurrState, NextState;
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@ -140,20 +138,6 @@ module cachefsm
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STATE_FLUSH_WRITE_BACK: if(CacheBusAck & ~(FlushFlag & FlushWayFlag)) NextState = STATE_FLUSH;
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else if(CacheBusAck) NextState = STATE_READY;
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else NextState = STATE_FLUSH_WRITE_BACK;
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/* -----\/----- EXCLUDED -----\/-----
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STATE_FLUSH: NextState = STATE_FLUSH_CHECK;
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STATE_FLUSH_CHECK: if(LineDirty) NextState = STATE_FLUSH_WRITE_BACK;
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else if(FlushFlag) NextState = STATE_READY;
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else if(FlushWayFlag) NextState = STATE_FLUSH_INCR;
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else NextState = STATE_FLUSH_CHECK;
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STATE_FLUSH_INCR: NextState = STATE_FLUSH_CHECK;
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STATE_FLUSH_WRITE_BACK: if(CacheBusAck) begin
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if(FlushFlag) NextState = STATE_READY;
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else if(FlushWayFlag) NextState = STATE_FLUSH_INCR;
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else NextState = STATE_FLUSH_CHECK;
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end else NextState = STATE_FLUSH_WRITE_BACK;
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-----/\----- EXCLUDED -----/\----- */
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default: NextState = STATE_READY;
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endcase
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end
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@ -180,11 +164,10 @@ module cachefsm
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// Flush and eviction controls
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assign SelWriteback = (CurrState == STATE_MISS_EVICT_DIRTY & ~CacheBusAck) |
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(CurrState == STATE_READY & AnyMiss & LineDirty);
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assign SelFlush = (CurrState == STATE_FLUSH) | (CurrState == STATE_FLUSH_CHECK) |
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(CurrState == STATE_FLUSH_INCR) | (CurrState == STATE_FLUSH_WRITE_BACK);
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assign FlushWayAndNotAdrFlag = FlushWayFlag & ~FlushAdrFlag;
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//assign FlushAdrCntEn = (CurrState == STATE_FLUSH_CHECK & ~LineDirty & FlushWayAndNotAdrFlag) |
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// (CurrState == STATE_FLUSH_WRITE_BACK & FlushWayAndNotAdrFlag & CacheBusAck);
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assign SelFlush = (CurrState == STATE_READY & FlushCache) |
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(CurrState == STATE_FLUSH & ~FlushFlag) |
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(CurrState == STATE_FLUSH_WRITE_BACK & ~(CacheBusAck & FlushFlag));
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assign FlushAdrCntEn = (CurrState == STATE_FLUSH_WRITE_BACK & FlushWayFlag & CacheBusAck) |
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(CurrState == STATE_FLUSH & FlushWayFlag & ~LineDirty);
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assign FlushWayCntEn = (CurrState == STATE_FLUSH & ~LineDirty) |
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@ -195,13 +178,9 @@ module cachefsm
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assign CacheBusRW[1] = (CurrState == STATE_READY & AnyMiss & ~LineDirty) |
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(CurrState == STATE_MISS_FETCH_WDV & ~CacheBusAck) |
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(CurrState == STATE_MISS_EVICT_DIRTY & CacheBusAck);
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// assign CacheBusRW[1] = CurrState == STATE_READY & AnyMiss;
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assign CacheBusRW[0] = (CurrState == STATE_READY & AnyMiss & LineDirty) |
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(CurrState == STATE_MISS_EVICT_DIRTY & ~CacheBusAck) |
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(CurrState == STATE_FLUSH_WRITE_BACK & ~CacheBusAck) |
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(CurrState == STATE_FLUSH_CHECK & LineDirty);
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// assign CacheBusRW[0] = (CurrState == STATE_MISS_FETCH_WDV & CacheBusAck & LineDirty) |
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// (CurrState == STATE_FLUSH_CHECK & VictimDirty);
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(CurrState == STATE_FLUSH_WRITE_BACK & ~CacheBusAck);
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// **** can this be simplified?
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assign SelAdr = (CurrState == STATE_READY & ((StoreAMO) & CacheHit)) | // changes if store delay hazard removed
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(CurrState == STATE_READY & (AnyMiss)) |
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