Xavi/cvw
1
0
Fork 0
forked from Github_Repos/cvw
Code Issues Pull Requests Packages Projects Releases Wiki Activity

Fixed RV32 tests after PMP fix

Browse Source
This commit is contained in:
David Harris 2023-03-28 08:35:23 -07:00
parent 39d3bf8e8a
commit aa31b45d88
8 changed files with 40 additions and 39 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
src/mmu/mmu.sv
View File

@ -108,12 +108,12 @@ module mmu #(parameter TLB_ENTRIES = 8, IMMU = 0) (
.Cacheable, .Idempotent, .SelTIM,
.PMAInstrAccessFaultF, .PMALoadAccessFaultM, .PMAStoreAmoAccessFaultM);
if (`PMP_ENTRIES > 0)
if (`PMP_ENTRIES > 0) begin : pmp
pmpchecker pmpchecker(.PhysicalAddress, .PrivilegeModeW,
.PMPCFG_ARRAY_REGW, .PMPADDR_ARRAY_REGW,
.ExecuteAccessF, .WriteAccessM, .ReadAccessM,
.PMPInstrAccessFaultF, .PMPLoadAccessFaultM, .PMPStoreAmoAccessFaultM);
else begin
end else begin
assign PMPInstrAccessFaultF = 0;
assign PMPStoreAmoAccessFaultM = 0;
assign PMPLoadAccessFaultM = 0;

3
src/mmu/pmpchecker.sv
View File

@ -56,7 +56,7 @@ module pmpchecker (
logic [`PMP_ENTRIES-1:0] L, X, W, R; // PMP matches and has flag set
logic [`PMP_ENTRIES-1:0] PAgePMPAdr; // for TOR PMP matching, PhysicalAddress > PMPAdr[i]
if (`PMP_ENTRIES > 0) // prevent complaints about array of no elements when PMP_ENTRIES = 0
if (`PMP_ENTRIES > 0) begin: pmp // prevent complaints about array of no elements when PMP_ENTRIES = 0
pmpadrdec pmpadrdecs[`PMP_ENTRIES-1:0](
.PhysicalAddress,
.PMPCfg(PMPCFG_ARRAY_REGW),
@ -64,6 +64,7 @@ module pmpchecker (
.PAgePMPAdrIn({PAgePMPAdr[`PMP_ENTRIES-2:0], 1'b1}),
.PAgePMPAdrOut(PAgePMPAdr),
.Match, .L, .X, .W, .R);
end
priorityonehot #(`PMP_ENTRIES) pmppriority(.a(Match), .y(FirstMatch)); // combine the match signal from all the adress decoders to find the first one that matches.

12
tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-trap-01.reference_output
View File

@ -6,16 +6,16 @@
00000000 # mtval of faulting instruction (0x0)
00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0
00000003 # mcause from Breakpoint
8000015c # mtval of breakpoint instruction adress
80000168 # mtval of breakpoint instruction adress
00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0
00000004 # mcause from load address misaligned
80000165 # mtval of misaligned address
80000171 # mtval of misaligned address
00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0
00000005 # mcause from load access
00000000 # mtval of accessed adress (0x0)
00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0
00000006 # mcause from store misaligned
8000017d # mtval of address with misaligned store instr
80000189 # mtval of address with misaligned store instr
00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0
00000007 # mcause from store access
00000000 # mtval of accessed address (0x0)
@ -62,16 +62,16 @@ fffff7ff # medeleg after attempted write of all 1's (only some bits are writeabl
00000000 # mtval of faulting instruction (0x0)
00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0
00000003 # mcause from Breakpoint
8000015c # mtval of breakpoint instruction adress
80000168 # mtval of breakpoint instruction adress
00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0
00000004 # mcause from load address misaligned
80000165 # mtval of misaligned address
80000171 # mtval of misaligned address
00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0
00000005 # mcause from load access
00000000 # mtval of accessed adress (0x0)
00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0
00000006 # mcause from store misaligned
8000017d # mtval of address with misaligned store instr
80000189 # mtval of address with misaligned store instr
00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0
00000007 # mcause from store access
00000000 # mtval of accessed address (0x0)

12
tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-trap-s-01.reference_output
View File

@ -9,16 +9,16 @@
00000000 # stval of faulting instruction (0x0)
00000800 # masked out mstatus.mpp = 1, mstatus.MPIE = 0, and mstatus.MIE = 0
00000003 # scause from Breakpoint
8000015c # stval of breakpoint instruction adress
80000168 # stval of breakpoint instruction adress
00000800 # masked out mstatus.mpp = 1, mstatus.MPIE = 0, and mstatus.MIE = 0
00000004 # scause from load address misaligned
80000165 # stval of misaligned address
80000171 # stval of misaligned address
00000800 # masked out mstatus.mpp = 1, mstatus.MPIE = 0, and mstatus.MIE = 0
00000005 # scause from load access
00000000 # stval of accessed adress (0x0)
00000800 # masked out mstatus.mpp = 1, mstatus.MPIE = 0, and mstatus.MIE = 0
00000006 # scause from store misaligned
8000017d # stval of address with misaligned store instr
80000189 # stval of address with misaligned store instr
00000800 # masked out mstatus.mpp = 1, mstatus.MPIE = 0, and mstatus.MIE = 0
00000007 # scause from store access
00000000 # stval of accessed address (0x0)
@ -60,16 +60,16 @@ fffff7ff # medeleg after attempted write of all 1's (only some bits are writeabl
00000000 # stval of faulting instruction (0x0)
00000120 # masked out sstatus.SPP = 1, sstatus.SPIE = 1, and sstatus.SIE = 0
00000003 # scause from Breakpoint
8000015c # stval of breakpoint instruction adress
80000168 # stval of breakpoint instruction adress
00000120 # masked out sstatus.SPP = 1, sstatus.SPIE = 1, and sstatus.SIE = 0
00000004 # scause from load address misaligned
80000165 # stval of misaligned address
80000171 # stval of misaligned address
00000120 # masked out sstatus.SPP = 1, sstatus.SPIE = 1, and sstatus.SIE = 0
00000005 # scause from load access
00000000 # stval of accessed adress (0x0)
00000120 # masked out sstatus.SPP = 1, sstatus.SPIE = 1, and sstatus.SIE = 0
00000006 # scause from store misaligned
8000017d # stval of address with misaligned store instr
80000189 # stval of address with misaligned store instr
00000120 # masked out sstatus.SPP = 1, sstatus.SPIE = 1, and sstatus.SIE = 0
00000007 # scause from store access
00000000 # stval of accessed address (0x0)

12
tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-trap-u-01.reference_output
View File

@ -9,16 +9,16 @@
00000000 # stval of faulting instruction (0x0)
00000000 # masked out mstatus.mpp = 0, mstatus.MPIE = 0, and mstatus.MIE = 0
00000003 # scause from Breakpoint
8000015c # stval of breakpoint instruction adress
80000168 # stval of breakpoint instruction adress
00000000 # masked out mstatus.mpp = 0, mstatus.MPIE = 0, and mstatus.MIE = 0
00000004 # scause from load address misaligned
80000165 # stval of misaligned address
80000171 # stval of misaligned address
00000000 # masked out mstatus.mpp = 0, mstatus.MPIE = 0, and mstatus.MIE = 0
00000005 # scause from load access
00000000 # stval of accessed adress (0x0)
00000000 # masked out mstatus.mpp = 0, mstatus.MPIE = 0, and mstatus.MIE = 0
00000006 # scause from store misaligned
8000017d # stval of address with misaligned store instr
80000189 # stval of address with misaligned store instr
00000000 # masked out mstatus.mpp = 0, mstatus.MPIE = 0, and mstatus.MIE = 0
00000007 # scause from store access
00000000 # stval of accessed address (0x0)
@ -57,16 +57,16 @@ fffff7ff # medeleg after attempted write of all 1's (only some bits are writeabl
00000000 # stval of faulting instruction (0x0)
00000020 # masked out sstatus.SPP = 0, sstatus.SPIE = 1, and sstatus.SIE = 0
00000003 # scause from Breakpoint
8000015c # stval of breakpoint instruction adress
80000168 # stval of breakpoint instruction adress
00000020 # masked out sstatus.SPP = 0, sstatus.SPIE = 1, and sstatus.SIE = 0
00000004 # scause from load address misaligned
80000165 # stval of misaligned address
80000171 # stval of misaligned address
00000020 # masked out sstatus.SPP = 0, sstatus.SPIE = 1, and sstatus.SIE = 0
00000005 # scause from load access
00000000 # stval of accessed adress (0x0)
00000020 # masked out sstatus.SPP = 0, sstatus.SPIE = 1, and sstatus.SIE = 0
00000006 # scause from store misaligned
8000017d # stval of address with misaligned store instr
80000189 # stval of address with misaligned store instr
00000020 # masked out sstatus.SPP = 0, sstatus.SPIE = 1, and sstatus.SIE = 0
00000007 # scause from store access
00000000 # stval of accessed address (0x0)

12
tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-trap-01.reference_output
View File

@ -14,13 +14,13 @@
00000000
00000003 # mcause from Breakpoint
00000000
800003f4 # mtval of breakpoint instruction adress (0x80000400)
80000408 # mtval of breakpoint instruction adress (0x80000400)
00000000
00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0
00000000
00000004 # mcause from load address misaligned
00000000
800003fd # mtval of misaligned address (0x80000409)
80000411 # mtval of misaligned address (0x80000409)
00000000
00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0
00000000
@ -32,7 +32,7 @@
00000000
00000006 # mcause from store misaligned
00000000
80000415 # mtval of address with misaligned store instr (0x80000421)
80000429 # mtval of address with misaligned store instr (0x80000421)
00000000
00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0
00000000
@ -126,13 +126,13 @@ ffffffff
00000000
00000003 # mcause from Breakpoint
00000000
800003f4 # mtval of breakpoint instruction adress (0x80000400)
80000408 # mtval of breakpoint instruction adress (0x80000400)
00000000
00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0
00000000
00000004 # mcause from load address misaligned
00000000
800003fd # mtval of misaligned address (0x80000409)
80000411 # mtval of misaligned address (0x80000409)
00000000
00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0
00000000
@ -144,7 +144,7 @@ ffffffff
00000000
00000006 # mcause from store misaligned
00000000
80000415 # mtval of address with misaligned store instr (0x80000421)
80000429 # mtval of address with misaligned store instr (0x80000421)
00000000
00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0
00000000

12
tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-trap-s-01.reference_output
View File

@ -20,13 +20,13 @@
00000000
00000003 # scause from Breakpoint
00000000
800003f4 # stval of breakpoint instruction adress (0x80000400)
80000408 # stval of breakpoint instruction adress (0x80000400)
00000000
00000800 # masked out mstatus.mpp = 1, mstatus.MPIE = 0, and mstatus.MIE = 0
00000000
00000004 # scause from load address misaligned
00000000
800003fd # stval of misaligned address (0x80000409)
80000411 # stval of misaligned address (0x80000409)
00000000
00000800 # masked out mstatus.mpp = 1, mstatus.MPIE = 0, and mstatus.MIE = 0
00000000
@ -38,7 +38,7 @@
00000000
00000006 # scause from store misaligned
00000000
80000415 # stval of address with misaligned store instr (0x80000421)
80000429 # stval of address with misaligned store instr (0x80000421)
00000000
00000800 # masked out mstatus.mpp = 1, mstatus.MPIE = 0, and mstatus.MIE = 0
00000000
@ -122,13 +122,13 @@ ffffffff
00000000
00000003 # scause from Breakpoint
00000000
800003f4 # stval of breakpoint instruction adress (0x80000400)
80000408 # stval of breakpoint instruction adress (0x80000400)
00000000
00000120 # masked out sstatus.SPP = 1, sstatus.SPIE = 1, and sstatus.SIE = 0
00000000
00000004 # scause from load address misaligned
00000000
800003fd # stval of misaligned address (0x80000409)
80000411 # stval of misaligned address (0x80000409)
00000000
00000120 # masked out sstatus.SPP = 1, sstatus.SPIE = 1, and sstatus.SIE = 0
00000000
@ -140,7 +140,7 @@ ffffffff
00000000
00000006 # scause from store misaligned
00000000
80000415 # stval of address with misaligned store instr (0x80000421)
80000429 # stval of address with misaligned store instr (0x80000421)
00000000
00000120 # masked out sstatus.SPP = 1, sstatus.SPIE = 1, and sstatus.SIE = 0
00000000

12
tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-trap-u-01.reference_output
View File

@ -20,13 +20,13 @@
00000000
00000003 # scause from Breakpoint
00000000
800003f4 # stval of breakpoint instruction adress (0x80000400)
80000408 # stval of breakpoint instruction adress (0x80000400)
00000000
00000000 # masked out mstatus.mpp = 0, mstatus.MPIE = 0, and mstatus.MIE = 0
00000000
00000004 # scause from load address misaligned
00000000
800003fd # stval of misaligned address (0x80000409)
80000411 # stval of misaligned address (0x80000409)
00000000
00000000 # masked out mstatus.mpp = 0, mstatus.MPIE = 0, and mstatus.MIE = 0
00000000
@ -38,7 +38,7 @@
00000000
00000006 # scause from store misaligned
00000000
80000415 # stval of address with misaligned store instr (0x80000421)
80000429 # stval of address with misaligned store instr (0x80000421)
00000000
00000000 # masked out mstatus.mpp = 0, mstatus.MPIE = 0, and mstatus.MIE = 0
00000000
@ -116,13 +116,13 @@ ffffffff
00000000
00000003 # scause from Breakpoint
00000000
800003f4 # stval of breakpoint instruction adress (0x80000400)
80000408 # stval of breakpoint instruction adress (0x80000400)
00000000
00000020 # masked out sstatus.SPP = 0, sstatus.SPIE = 1, and sstatus.SIE = 0
00000000
00000004 # scause from load address misaligned
00000000
800003fd # stval of misaligned address (0x80000409)
80000411 # stval of misaligned address (0x80000409)
00000000
00000020 # masked out sstatus.SPP = 0, sstatus.SPIE = 1, and sstatus.SIE = 0
00000000
@ -134,7 +134,7 @@ ffffffff
00000000
00000006 # scause from store misaligned
00000000
80000415 # stval of address with misaligned store instr (0x80000421)
80000429 # stval of address with misaligned store instr (0x80000421)
00000000
00000020 # masked out sstatus.SPP = 0, sstatus.SPIE = 1, and sstatus.SIE = 0
00000000