Removed unused flushf.

pipelined/src/hazard/hazard.sv

@@ -41,7 +41,7 @@ module hazard(
 (* mark_debug = "true" *)        input logic  wfiM, IntPendingM,
   // Stall & flush outputs
 (* mark_debug = "true" *)	      output logic StallF, StallD, StallE, StallM, StallW,
-(* mark_debug = "true" *)	      output logic FlushF, FlushD, FlushE, FlushM, FlushW
+(* mark_debug = "true" *)	      output logic FlushD, FlushE, FlushM, FlushW
 );
 
   logic StallFCause, StallDCause, StallECause, StallMCause, StallWCause;
@@ -89,7 +89,6 @@ module hazard(
   assign FirstUnstalledW = ~StallW & StallM;
   
   // Each stage flushes if the previous stage is the last one stalled (for cause) or the system has reason to flush
-  assign #1 FlushF = BPPredWrongE;
   assign #1 FlushD = FirstUnstalledD | TrapM | RetM | BPPredWrongE; 
   assign #1 FlushE = FirstUnstalledE | TrapM | RetM | BPPredWrongE; // *** why is BPPredWrongE here, but not needed in simple processor 
   assign #1 FlushM = FirstUnstalledM | TrapM | RetM;

pipelined/src/ifu/bpred.sv

@@ -36,7 +36,7 @@
 module bpred 
   (input logic              clk, reset,
    input logic              StallF, StallD, StallE, StallM,
-   input logic              FlushF, FlushD, FlushE, FlushM,
+   input logic              FlushD, FlushE, FlushM,
    // Fetch stage
    // the prediction
    input logic [31:0]       InstrD, 
@@ -103,7 +103,7 @@ module bpred
   else if (`BPTYPE == "BPLOCALPAg") begin:Predictor
 
     localHistoryPredictor DirPredictor(.clk,
-      .reset, .StallF, .StallE, .FlushF,
+      .reset, .StallF, .StallE,
       .LookUpPC(PCNextF),
       .Prediction(BPPredF),
       // update

pipelined/src/ifu/ifu.sv

@@ -34,7 +34,7 @@
 module ifu (
 	input logic 				clk, reset,
 	input logic 				StallF, StallD, StallE, StallM, 
-	input logic 				FlushF, FlushD, FlushE, FlushM, FlushW, 
+	input logic 				FlushD, FlushE, FlushM, FlushW, 
 	// Bus interface
 (* mark_debug = "true" *)	input logic [`XLEN-1:0] 	HRDATA,
 (* mark_debug = "true" *)	output logic [`PA_BITS-1:0] IFUHADDR,
@@ -309,7 +309,7 @@ module ifu (
     logic [`XLEN-1:0]            BPPredPCF;
     bpred bpred(.clk, .reset,
                 .StallF, .StallD, .StallE, .StallM, 
-                .FlushF, .FlushD, .FlushE, .FlushM,
+                .FlushD, .FlushE, .FlushM,
                 .InstrD, .PCNextF, .BPPredPCF, .SelBPPredF, .PCE, .PCSrcE, .IEUAdrE,
                 .PCD, .PCLinkE, .InstrClassM, .BPPredWrongE, .BPPredWrongM, 
                 .BPPredDirWrongM, .BTBPredPCWrongM, .RASPredPCWrongM, .BPPredClassNonCFIWrongM);

pipelined/src/ifu/localHistoryPredictor.sv

@@ -38,7 +38,7 @@ module localHistoryPredictor
       )
   (input logic             clk,
    input logic             reset,
-   input logic             StallF,  StallE, FlushF,
+   input logic             StallF,  StallE,
    input logic [`XLEN-1:0] LookUpPC,
    output logic [1:0]      Prediction,
    // update
@@ -116,7 +116,7 @@ module localHistoryPredictor
   flopenrc #(k) LHRFReg(.clk(clk),
    .reset(reset),
    .en(~StallF),
-   .clear(FlushF),
+   .clear(1'b0),
    .d(ForwardLHRNext),
    .q(LHRF));
   /*

pipelined/src/wally/wallypipelinedcore.sv

@@ -53,7 +53,7 @@ module wallypipelinedcore (
 
   //  logic [1:0]  ForwardAE, ForwardBE;
   logic             StallF, StallD, StallE, StallM, StallW;
-  logic             FlushF, FlushD, FlushE, FlushM, FlushW;
+  logic             FlushD, FlushE, FlushM, FlushW;
   logic             RetM;
   (* mark_debug = "true" *) logic TrapM;
 
@@ -170,7 +170,7 @@ module wallypipelinedcore (
   ifu ifu(
     .clk, .reset,
     .StallF, .StallD, .StallE, .StallM, 
-    .FlushF, .FlushD, .FlushE, .FlushM, .FlushW,
+    .FlushD, .FlushE, .FlushM, .FlushW,
     // Fetch
     .HRDATA, .PCF, .IFUHADDR,
     .IFUStallF, .IFUHBURST, .IFUHTRANS, .IFUHSIZE,
@@ -325,7 +325,7 @@ module wallypipelinedcore (
      .wfiM, .IntPendingM,
      // Stall & flush outputs
     .StallF, .StallD, .StallE, .StallM, .StallW,
-    .FlushF, .FlushD, .FlushE, .FlushM, .FlushW
+    .FlushD, .FlushE, .FlushM, .FlushW
      );    // global stall and flush control
 
    if (`ZICSR_SUPPORTED) begin:priv