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Merge remote-tracking branch 'upstream/main'
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Ross Thompson
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README.md
42
README.md
@ -7,39 +7,55 @@ Wally is a 5-stage pipelined processor configurable to support all the standard
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Wally is described in a textbook, RISC-V System-on-Chip Design, by Harris, Stine, Thompson, and Harris. Users should follow the setup instructions below. A system administrator must install CAD tools using the directions further down.
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# New User Setup
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New users may wish to do the following setup to access the server via a GUI and use a text editor.
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Download and install x2go - A.1.1
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Download and install VSCode - A.4.2
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Make sure you can log into Tera acceptly via x2go and via a terminal
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Optional: Download and install x2go - A.1.1
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Optional: Download and install VSCode - A.4.2
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Optional: Make sure you can log into your server via x2go and via a terminal
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Terminal on Mac, cmd on Windows, xterm on Linux
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See A.1 about ssh -Y login from a terminal
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Git started with Git configuration and authentication: B.1
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$ git config --global user.name ″Ben Bitdiddle″
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$ git config --global user.email ″ben_bitdiddle@wally.edu″
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$ git config --global pull.rebase false
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Then follow Section 2.2 to clone the repo, source setup, make the tests and run regression
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Then clone the repo, source setup, make the tests and run regression
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If you don't already have a Github account, create one
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In a web browser, visit https://github.com/openhwgroup/cvw
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In the upper right part of the screen, click on Fork
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Create a fork, choosing the owner as your github account and the repository as cvw.
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On the Linux computer where you will be working, log in, clone your fork of the repo,
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run the setup script, and build the tests:
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On the Linux computer where you will be working, log in
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Add the following lines to your .bashrc or .bash_profile to run the setup script each time you log in.
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if [ -f ~/cvw/setup.sh ]; then
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source ~/cvw/setup.sh
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fi
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Clone your fork of the repo, run the setup script, and build the tests:
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$ cd
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$ git clone --recurse-submodules https://github.com/<yourgithubid>/cvw
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$ cd cvw
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$ source ./setup.sh
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$ make
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Edit setup.sh and change the following lines to point to the path and license server for your Siemens Questa and Synopsys Design Compiler installation and license server. If you only have Questa, you can still simulate but cannot run logic synthesis.
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export MGLS_LICENSE_FILE=1717@solidworks.eng.hmc.edu # Change this to your Siemens license server
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export SNPSLMD_LICENSE_FILE=27020@zircon.eng.hmc.edu # Change this to your Synopsys license server
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export QUESTAPATH=/cad/mentor/questa_sim-2021.2_1/questasim/bin # Change this for your path to Questa
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export SNPSPATH=/cad/synopsys/SYN/bin # Change this for your path to Design Compiler
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Run a regression simulation with Questa to prove everything is installed.
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$ cd pipelined/regression
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$ ./regression-wally (depends on having Questa installed)
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Add the following lines to your .bashrc or .bash_profile
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if [ -f ~/cvw/setup.sh ]; then
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source ~/cvw/setup.sh
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fi
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# Tool-chain Installation (Sys Admin)
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This section describes the open source toolchain installation. These steps should only be done once by the system admin.
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@ -49,7 +65,7 @@ This section describes the open source toolchain installation. These steps shou
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The full instalation details are involved can be be skipped using the following script, wally-tool-chain-install.sh.
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The script installs the open source tools to /opt/riscv by default. This can be changed by supply the path as the first argument. This script does not install buildroot (see the Detailed Tool-chain Install Guide in the following section) and does not install commercial EDA tools; Siemens Questa, Synopsys Design Compiler, or Cadence Innovus (see section Installing IDA Tools). It must be run as root or with sudo. This script is tested for Ubuntu, 20.04 and 22.04. Fedora and Red Hat can be installed in the Detailed Tool-chain Install Guide.
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$ wally-tool-chain-install.sh <optional, install directory, defaults to /opt/riscv>
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$ sudo wally-tool-chain-install.sh <optional, install directory, defaults to /opt/riscv>
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## Detailed Tool-chain Install Guide
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@ -1,136 +0,0 @@
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// V. G. Oklobdzija, "Algorithmic design of a hierarchical and modular
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// leading zero detector circuit," in Electronics Letters, vol. 29,
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// no. 3, pp. 283-284, 4 Feb. 1993, doi: 10.1049/el:19930193.
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module lz2 (P, V, B0, B1);
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input logic B0;
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input logic B1;
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output logic P;
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output logic V;
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assign V = B0 | B1;
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assign P = B0 & ~B1;
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endmodule // lz2
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// Note: This module is not made out of two lz2's - why not? (MJS)
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module lz4 (ZP, ZV, B0, B1, V0, V1);
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output logic [1:0] ZP;
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output logic ZV;
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input logic B0;
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input logic B1;
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input logic V0;
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input logic V1;
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assign ZP[0] = V0 ? B0 : B1;
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assign ZP[1] = ~V0;
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assign ZV = V0 | V1;
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endmodule // lz4
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// Note: This module is not made out of two lz4's - why not? (MJS)
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module lz8 (ZP, ZV, B);
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input logic [7:0] B;
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output logic [2:0] ZP;
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output logic ZV;
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logic s1p0;
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logic s1v0;
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logic s1p1;
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logic s1v1;
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logic s2p0;
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logic s2v0;
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logic s2p1;
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logic s2v1;
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logic [1:0] ZPa;
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logic [1:0] ZPb;
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logic ZVa;
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logic ZVb;
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lz2 l1(s1p0, s1v0, B[2], B[3]);
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lz2 l2(s1p1, s1v1, B[0], B[1]);
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lz4 l3(ZPa, ZVa, s1p0, s1p1, s1v0, s1v1);
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lz2 l4(s2p0, s2v0, B[6], B[7]);
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lz2 l5(s2p1, s2v1, B[4], B[5]);
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lz4 l6(ZPb, ZVb, s2p0, s2p1, s2v0, s2v1);
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assign ZP[1:0] = ZVb ? ZPb : ZPa;
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assign ZP[2] = ~ZVb;
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assign ZV = ZVa | ZVb;
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endmodule // lz8
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module lz16 (ZP, ZV, B);
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input logic [15:0] B;
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output logic [3:0] ZP;
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output logic ZV;
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logic [2:0] ZPa;
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logic [2:0] ZPb;
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logic ZVa;
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logic ZVb;
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lz8 l1(ZPa, ZVa, B[7:0]);
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lz8 l2(ZPb, ZVb, B[15:8]);
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assign ZP[2:0] = ZVb ? ZPb : ZPa;
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assign ZP[3] = ~ZVb;
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assign ZV = ZVa | ZVb;
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endmodule // lz16
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module lz32 (ZP, ZV, B);
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input logic [31:0] B;
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output logic [4:0] ZP;
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output logic ZV;
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logic [3:0] ZPa;
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logic [3:0] ZPb;
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logic ZVa;
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logic ZVb;
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lz16 l1(ZPa, ZVa, B[15:0]);
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lz16 l2(ZPb, ZVb, B[31:16]);
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assign ZP[3:0] = ZVb ? ZPb : ZPa;
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assign ZP[4] = ~ZVb;
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assign ZV = ZVa | ZVb;
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endmodule // lz32
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// This module returns the number of leading zeros ZP in the 64-bit
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// number B. If there are no ones in B, then ZP and ZV are both 0.
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module lz64 (ZP, ZV, B);
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input logic [63:0] B;
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output logic [5:0] ZP;
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output logic ZV;
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logic [4:0] ZPa;
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logic [4:0] ZPb;
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logic ZVa;
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logic ZVb;
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lz32 l1(ZPa, ZVa, B[31:0]);
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lz32 l2(ZPb, ZVb, B[63:32]);
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assign ZV = ZVa | ZVb;
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assign ZP[4:0] = (ZVb ? ZPb : ZPa) & {5{ZV}};
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assign ZP[5] = ~ZVb & ZV;
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endmodule // lz64
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@ -47,7 +47,7 @@ module wallypipelinedcore (
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output logic [3:0] HPROT,
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output logic [1:0] HTRANS,
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output logic HMASTLOCK
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);
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);
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logic StallF, StallD, StallE, StallM, StallW;
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logic FlushD, FlushE, FlushM, FlushW;
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