forked from Github_Repos/cvw
Coverage improvement: ieu, hazard, priv
This commit is contained in:
David Harris
commit
03b4f6660c
@ -146,10 +146,13 @@ module fctrl (
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ControlsD = `FCTRLW'b1_0_01_00_000_0_0_0; // fcvt.s.(d/q/h)
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7'b0100001: if (Rs2D[4:2] == 3'b000 & SupportedFmt2 & Rs2D[1:0] != 2'b01)
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ControlsD = `FCTRLW'b1_0_01_00_001_0_0_0; // fcvt.d.(s/h/q)
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// coverage off
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// Not covered in testing because rv64gc does not support half or quad precision
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7'b0100010: if (Rs2D[4:2] == 3'b000 & SupportedFmt2 & Rs2D[1:0] != 2'b10)
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ControlsD = `FCTRLW'b1_0_01_00_010_0_0_0; // fcvt.h.(s/d/q)
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7'b0100011: if (Rs2D[4:2] == 3'b000 & SupportedFmt2 & Rs2D[1:0] != 2'b11)
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ControlsD = `FCTRLW'b1_0_01_00_011_0_0_0; // fcvt.q.(s/h/d)
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// coverage on
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7'b1101000: case(Rs2D)
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5'b00000: ControlsD = `FCTRLW'b1_0_01_00_101_0_0_0; // fcvt.s.w w->s
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5'b00001: ControlsD = `FCTRLW'b1_0_01_00_100_0_0_0; // fcvt.s.wu wu->s
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@ -174,6 +177,8 @@ module fctrl (
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5'b00010: ControlsD = `FCTRLW'b0_1_01_00_011_0_0_1; // fcvt.l.d d->l
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5'b00011: ControlsD = `FCTRLW'b0_1_01_00_010_0_0_1; // fcvt.lu.d d->lu
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endcase
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// coverage off
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// Not covered in testing because rv64gc does not support half or quad precision
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7'b1101010: case(Rs2D)
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5'b00000: ControlsD = `FCTRLW'b1_0_01_00_101_0_0_0; // fcvt.h.w w->h
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5'b00001: ControlsD = `FCTRLW'b1_0_01_00_100_0_0_0; // fcvt.h.wu wu->h
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@ -198,7 +203,7 @@ module fctrl (
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5'b00010: ControlsD = `FCTRLW'b0_1_01_00_011_0_0_1; // fcvt.l.q q->l
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5'b00011: ControlsD = `FCTRLW'b0_1_01_00_010_0_0_1; // fcvt.lu.q q->lu
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endcase
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// coverage on
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endcase
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endcase
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end
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@ -329,4 +334,4 @@ module fctrl (
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{FRegWriteM, FResSelM, FCvtIntM},
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{FRegWriteW, FResSelW, FCvtIntW});
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endmodule
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endmodule
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@ -37,7 +37,7 @@ module alu #(parameter WIDTH=32) (
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input logic [1:0] BSelect, // Binary encoding of if it's a ZBA_ZBB_ZBC_ZBS instruction
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input logic [2:0] ZBBSelect, // ZBB mux select signal
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input logic [2:0] Funct3, // For BMU decoding
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input logic [1:0] CompFlags, // Comparator flags
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input logic CompLT, // Less-Than flag from comparator
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input logic [2:0] BALUControl, // ALU Control signals for B instructions in Execute Stage
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output logic [WIDTH-1:0] Result, // ALU result
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output logic [WIDTH-1:0] Sum); // Sum of operands
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@ -90,7 +90,7 @@ module alu #(parameter WIDTH=32) (
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// Final Result B instruction select mux
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if (`ZBC_SUPPORTED | `ZBS_SUPPORTED | `ZBA_SUPPORTED | `ZBB_SUPPORTED) begin : bitmanipalu
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bitmanipalu #(WIDTH) balu(.A, .B, .W64, .BSelect, .ZBBSelect,
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.Funct3, .CompFlags, .BALUControl, .ALUResult, .FullResult,
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.Funct3, .CompLT, .BALUControl, .ALUResult, .FullResult,
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.CondMaskB, .CondShiftA, .Result);
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end else begin
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assign Result = ALUResult;
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@ -35,7 +35,7 @@ module bitmanipalu #(parameter WIDTH=32) (
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input logic [1:0] BSelect, // Binary encoding of if it's a ZBA_ZBB_ZBC_ZBS instruction
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input logic [2:0] ZBBSelect, // ZBB mux select signal
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input logic [2:0] Funct3, // Funct3 field of opcode indicates operation to perform
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input logic [1:0] CompFlags, // Comparator flags
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input logic CompLT, // Less-Than flag from comparator
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input logic [2:0] BALUControl, // ALU Control signals for B instructions in Execute Stage
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input logic [WIDTH-1:0] ALUResult, FullResult, // ALUResult, FullResult signals
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output logic [WIDTH-1:0] CondMaskB, // B is conditionally masked for ZBS instructions
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@ -84,7 +84,7 @@ module bitmanipalu #(parameter WIDTH=32) (
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// ZBB Unit
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if (`ZBB_SUPPORTED) begin: zbb
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zbb #(WIDTH) ZBB(.A, .RevA, .B, .ALUResult, .W64, .lt(CompFlags[0]), .ZBBSelect, .ZBBResult);
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zbb #(WIDTH) ZBB(.A, .RevA, .B, .W64, .lt(CompLT), .ZBBSelect, .ZBBResult);
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end else assign ZBBResult = 0;
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// Result Select Mux
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@ -32,7 +32,7 @@
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module cnt #(parameter WIDTH = 32) (
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input logic [WIDTH-1:0] A, RevA, // Operands
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input logic [4:0] B, // Last 5 bits of immediate
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input logic [1:0] B, // Last 2 bits of immediate
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input logic W64, // Indicates word operation
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output logic [WIDTH-1:0] CntResult // count result
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);
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@ -32,18 +32,17 @@
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module zbb #(parameter WIDTH=32) (
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input logic [WIDTH-1:0] A, RevA, B, // Operands
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input logic [WIDTH-1:0] ALUResult, // ALU Result
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input logic W64, // Indicates word operation
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input logic lt, // lt flag
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input logic [2:0] ZBBSelect, // Indicates word operation
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input logic [2:0] ZBBSelect, // ZBB Result select signal
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output logic [WIDTH-1:0] ZBBResult); // ZBB result
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logic [WIDTH-1:0] CntResult; // count result
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logic [WIDTH-1:0] MinMaxResult; // min,max result
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logic [WIDTH-1:0] MinMaxResult; // min, max result
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logic [WIDTH-1:0] ByteResult; // byte results
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logic [WIDTH-1:0] ExtResult; // sign/zero extend results
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cnt #(WIDTH) cnt(.A, .RevA, .B(B[4:0]), .W64, .CntResult);
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cnt #(WIDTH) cnt(.A, .RevA, .B(B[1:0]), .W64, .CntResult);
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byteUnit #(WIDTH) bu(.A, .ByteSelect(B[0]), .ByteResult);
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ext #(WIDTH) ext(.A, .ExtSelect({~B[2], {B[2] & B[0]}}), .ExtResult);
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@ -114,7 +114,7 @@ module datapath (
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comparator #(`XLEN) comp(ForwardedSrcAE, ForwardedSrcBE, BranchSignedE, FlagsE);
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mux2 #(`XLEN) srcamux(ForwardedSrcAE, PCE, ALUSrcAE, SrcAE);
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mux2 #(`XLEN) srcbmux(ForwardedSrcBE, ImmExtE, ALUSrcBE, SrcBE);
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alu #(`XLEN) alu(SrcAE, SrcBE, W64E, SubArithE, ALUSelectE, BSelectE, ZBBSelectE, Funct3E, FlagsE, BALUControlE, ALUResultE, IEUAdrE);
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alu #(`XLEN) alu(SrcAE, SrcBE, W64E, SubArithE, ALUSelectE, BSelectE, ZBBSelectE, Funct3E, FlagsE[0], BALUControlE, ALUResultE, IEUAdrE);
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mux2 #(`XLEN) altresultmux(ImmExtE, PCLinkE, JumpE, AltResultE);
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mux2 #(`XLEN) ieuresultmux(ALUResultE, AltResultE, ALUResultSrcE, IEUResultE);
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@ -28,7 +28,7 @@
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main:
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bseti t0, zero, 14 # turn on FPU
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#bseti t0, zero, 14 # turn on FPU
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csrs mstatus, t0
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# Test legal instructions not covered elsewhere
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@ -36,6 +36,8 @@ main:
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flh ft0, 8(a0)
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fsq ft0, 0(a0)
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fsh ft0, 8(a0)
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# Tests for fpu/fctrl.sv
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fcvt.h.s ft1, ft0
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fcvt.q.s ft2, ft0
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fcvt.h.w ft3, a0
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@ -55,7 +57,6 @@ main:
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fcvt.l.q a0, ft3
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fcvt.lu.q a0, ft3
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# Test illegal instructions are detected
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.word 0x00000007 // illegal floating-point load (bad Funct3)
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.word 0x00000027 // illegal floating-point store (bad Funct3)
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@ -36,6 +36,7 @@ main:
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addi t0, zero, 0
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csrr t0, stimecmp
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<<<<<<< HEAD
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# CSR coverage
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csrw scause, zero
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csrw stval, zero
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@ -62,4 +63,13 @@ main:
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=======
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# Test write to STVAL, SCAUSE, SEPC, and STIMECMP CSRs
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li t0, 0
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csrw stval, t0
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csrw scause, t0
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csrw sepc, t0
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csrw stimecmp, t0
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>>>>>>> 37d289cf44530c3e3a6f53e54b06e6eda7f0c3c1
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j done
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