forked from Github_Repos/cvw
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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commit
7a139e0d71
@ -157,7 +157,7 @@ void softfloatInit(void) {
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// RM: softfloat_round_min
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softfloat_roundingMode = softfloat_round_near_even;
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softfloat_exceptionFlags = 0; // clear exceptions
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softfloat_detectTininess = softfloat_tininess_beforeRounding; // RISC-V behavior for tininess
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softfloat_detectTininess = softfloat_tininess_afterRounding; // RISC-V behavior for tininess
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}
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uint64_t parseNum(char *num) {
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@ -37,7 +37,7 @@ void softfloatInit(void) {
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// RM: softfloat_round_min
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softfloat_roundingMode = softfloat_round_near_even;
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softfloat_exceptionFlags = 0; // clear exceptions
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softfloat_detectTininess = softfloat_tininess_beforeRounding; // RISC-V behavior for tininess
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softfloat_detectTininess = softfloat_tininess_afterRounding; // RISC-V behavior for tininess
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}
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int main()
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@ -857,6 +857,7 @@ trap_handler_end_\MODE\(): // place to jump to so we can skip the trap handler a
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addi a6, a6, 8
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.endm
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// Place this macro in peripheral tests to setup all the PLIC registers to generate external interrupts
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.macro SETUP_PLIC
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# Setup PLIC with a series of register writes
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