clean up divshiftcalc

pipelined/src/fpu/divshiftcalc.sv

@@ -10,7 +10,9 @@ module divshiftcalc(
     output logic DivResDenorm,
     output logic [`NE+1:0] DivDenormShift
 );
-    logic [`NE+1:0] NormShift;
+    logic [`LOGNORMSHIFTSZ-1:0] NormShift, DivDenormShiftAmt;
+    //logic [`NE+1:0] DivDenormShift;
+    logic DivDenormShiftPos;
 
     logic [`DURLEN-1:0] DivEarlyTermShift = 0;
 
@@ -25,6 +27,8 @@ module divshiftcalc(
     //  .0000xxxxxxxxxxx... >> 1                Exp = 1
     // Left shift amount  = DivQe+NF+1-1
     assign DivDenormShift = (`NE+2)'(`NF)+DivQe;
+    assign DivDenormShiftPos = ~DivDenormShift[`NE+1];
+
     // if the result is normalized
     //  00000000x.xxxxxx...                     Exp = DivQe
     //  .00000000xxxxxxx... >> NF+1             Exp = DivQe+NF+1
@@ -33,12 +37,11 @@ module divshiftcalc(
     //  00000000xx.xxxxx... << 1?               Exp = DivQe-1 (determined after)
     // inital Left shift amount  = NF
     // shift one more if the it's a minimally redundent radix 4 - one entire cycle needed for integer bit
-    assign NormShift = (`NE+2)'(`NF);
-    // if the shift amount is negitive then dont shift (keep sticky bit)
+    assign NormShift = (`LOGNORMSHIFTSZ)'(`NF);
+    // if the shift amount is negitive then don't shift (keep sticky bit)
     // need to multiply the early termination shift by LOGR*DIVCOPIES =  left shift of log2(LOGR*DIVCOPIES)
-    assign DivShiftAmt = (DivResDenorm ?  DivDenormShift[`LOGNORMSHIFTSZ-1:0]&{`LOGNORMSHIFTSZ{~DivDenormShift[`NE+1]}} : NormShift[`LOGNORMSHIFTSZ-1:0])+{{`LOGNORMSHIFTSZ-`DURLEN-$clog2(`LOGR*`DIVCOPIES){1'b0}}, 
-    DivEarlyTermShift&{`DURLEN{~(DivDenormShift[`NE+1]|Sqrt)}}, {$clog2(`LOGR*`DIVCOPIES){1'b0}}};
+    assign DivDenormShiftAmt = DivDenormShift[`LOGNORMSHIFTSZ-1:0]&{`LOGNORMSHIFTSZ{DivDenormShiftPos}};
+    assign DivShiftAmt = DivResDenorm ? DivDenormShiftAmt : NormShift;
 
     assign DivShiftIn = {{`NF{1'b0}}, DivQm, {`NORMSHIFTSZ-`DIVb+1+(`RADIX/4)-`NF{1'b0}}};
-
 endmodule