forked from Github_Repos/cvw
Removed commented code.
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85366a287b
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13
pipelined/src/cache/cache.sv
vendored
13
pipelined/src/cache/cache.sv
vendored
@ -98,8 +98,6 @@ module cache #(parameter LINELEN, NUMLINES, NUMWAYS, LOGBWPL, WORDLEN, MUXINTE
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logic LRUWriteEn;
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logic SelFlush;
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logic ResetOrFlushAdr, ResetOrFlushWay;
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logic [NUMWAYS-1:0] SelectedWay;
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logic [NUMWAYS-1:0] SetValidWay, ClearValidWay, SetDirtyWay, ClearDirtyWay;
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logic [LINELEN-1:0] ReadDataLine, ReadDataLineCache;
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logic [$clog2(LINELEN/8) - $clog2(MUXINTERVAL/8) - 1:0] WordOffsetAddr;
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logic SelBusBuffer;
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@ -192,17 +190,6 @@ module cache #(parameter LINELEN, NUMLINES, NUMWAYS, LOGBWPL, WORDLEN, MUXINTE
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if(NUMWAYS > 1) assign NextFlushWay = {FlushWay[NUMWAYS-2:0], FlushWay[NUMWAYS-1]};
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else assign NextFlushWay = FlushWay[NUMWAYS-1];
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/////////////////////////////////////////////////////////////////////////////////////////////
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// Write Path: Write Enables
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/////////////////////////////////////////////////////////////////////////////////////////////
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/* -----\/----- EXCLUDED -----\/-----
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mux3 #(NUMWAYS) selectwaymux(HitWay, VictimWay, FlushWay, {SelFlush, SetValid}, SelectedWay);
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assign SetValidWay = SetValid ? SelectedWay : '0;
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assign ClearValidWay = ClearValid ? SelectedWay : '0;
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assign SetDirtyWay = SetDirty ? SelectedWay : '0;
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assign ClearDirtyWay = ClearDirty ? SelectedWay : '0;
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-----/\----- EXCLUDED -----/\----- */
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/////////////////////////////////////////////////////////////////////////////////////////////
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// Cache FSM
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/////////////////////////////////////////////////////////////////////////////////////////////
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