forked from Github_Repos/cvw
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
This commit is contained in:
Ross Thompson
commit
d1ce84d172
8
pipelined/src/cache/cache.sv
vendored
8
pipelined/src/cache/cache.sv
vendored
@ -117,13 +117,15 @@ module cache #(parameter LINELEN, NUMLINES, NUMWAYS, LOGBWPL, WORDLEN, MUXINTE
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/////////////////////////////////////////////////////////////////////////////////////////////
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// Choose read address (RAdr). Normally use NextAdr, but use PAdr during stalls
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// and FlushAdr when handling D$ flushes
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// and FlushAdr when handling D$ flushes
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// The icache must update to the newest PCNextF on flush as it is probably a trap. Trap
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// sets PCNextF to XTVEC and the icache must start reading the instruction.
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mux3 #(SETLEN) AdrSelMux(
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.d0(NextAdr[SETTOP-1:OFFSETLEN]), .d1(PAdr[SETTOP-1:OFFSETLEN]), .d2(FlushAdr),
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.s({SelFlush, (SelAdr | SelHPTW)}), .y(RAdr));
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.s({SelFlush, ((SelAdr | SelHPTW) & ~((DCACHE == 0) & FlushStage))}), .y(RAdr));
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// Array of cache ways, along with victim, hit, dirty, and read merging logic
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cacheway #(NUMLINES, LINELEN, TAGLEN, OFFSETLEN, SETLEN)
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cacheway #(NUMLINES, LINELEN, TAGLEN, OFFSETLEN, SETLEN, DCACHE)
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CacheWays[NUMWAYS-1:0](.clk, .reset, .ce(SRAMEnable), .RAdr, .PAdr, .LineWriteData, .LineByteMask,
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.SetValidWay, .ClearValidWay, .SetDirtyWay, .ClearDirtyWay, .SelEvict, .VictimWay,
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.FlushWay, .SelFlush, .ReadDataLineWay, .HitWay, .VictimDirtyWay, .VictimTagWay, .FlushStage,
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105
pipelined/src/cache/cachereplacementpolicy.sv
vendored
105
pipelined/src/cache/cachereplacementpolicy.sv
vendored
@ -46,10 +46,115 @@ module cachereplacementpolicy
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logic [SETLEN-1:0] RAdrD;
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logic LRUWriteEnD;
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localparam LOGNUMWAYS = $clog2(NUMWAYS);
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localparam LEN = NUMWAYS-1;
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logic [LOGNUMWAYS-1:0] HitWayEnc;
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logic [LEN-1:0] HitWayExpand;
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genvar row;
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logic [NUMWAYS-2:0] cEn;
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/* -----\/----- EXCLUDED -----\/-----
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// proposed generic solution
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binencoder #(NUMWAYS) encoder(HitWay, HitWayEnc);
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// bit duplication
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// expand HitWay as HitWay[3], {{2}{HitWay[2]}}, {{4}{HitWay[1]}, {{8{HitWay[0]}}, ...
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for(row = 0; row < LOGNUMWAYS; row++) begin
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localparam integer DuplicationFactor = 2**(LOGNUMWAYS-row-1);
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localparam integer StartIndex = NUMWAYS-2 - DuplicationFactor + 1;
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localparam integer EndIndex = NUMWAYS-2 - 2 * DuplicationFactor + 2;
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assign HitWayExpand[StartIndex : EndIndex] = {{DuplicationFactor}{HitWayEnc[row]}};
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end
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genvar r, a,s;
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//localparam s = NUMWAYS-2;
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assign cEn[NUMWAYS-2] = '1;
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for(s = NUMWAYS-2; s >= NUMWAYS/2; s--) begin : enables
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localparam p = NUMWAYS - s;
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localparam g = $clog2(p);
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localparam t0 = s - g;
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localparam t1 = t0 - 1;
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localparam r = LOGNUMWAYS - g;
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assign cEn[t0] = cEn[s] & ~HitWayEnc[r];
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assign cEn[t1] = cEn[s] & HitWayEnc[r];
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end
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mux2 #(1) LRUMuxes[NUMWAYS-2:0](LineReplacementBits, HitWayExpand, cEn, NewReplacement);
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assign VictimWay[0] = ~LineReplacementBits[2] & ~LineReplacementBits[0];
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assign VictimWay[1] = ~LineReplacementBits[2] & LineReplacementBits[0];
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assign VictimWay[2] = LineReplacementBits[2] & ~LineReplacementBits[1];
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assign VictimWay[3] = LineReplacementBits[2] & LineReplacementBits[1];
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-----/\----- EXCLUDED -----/\----- */
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/* -----\/----- EXCLUDED -----\/-----
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// logic [NUMWAYS/2-1:0] rawEn [LOGNUMWAYS-1:0];
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for(r = LOGNUMWAYS-1; r >= 0; r--) begin
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localparam integer g = 2**(LOGNUMWAYS-r-1);
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for(a = g-1; a > 0; a--) begin
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localparam t0 = s - 2**(g-1);
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localparam t1 = t0 - 1;
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localparam s = s - 1;
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assign cEn[t0] = cEn[s] & ~HitWayEnc[r];
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assign cEn[t1] = cEn[s] & HitWayEnc[r];
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end
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-----/\----- EXCLUDED -----/\----- */
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/* -----\/----- EXCLUDED -----\/-----
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for(a = g-1; a > 0; a--) begin
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localparam t0 = s - 2**(g-1);
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localparam t1 = t0 - 1;
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s = s - 1;
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end
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end
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-----/\----- EXCLUDED -----/\----- */
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/* -----\/----- EXCLUDED -----\/-----
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always_comb begin
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for(r = LOGNUMWAYS-1; r > 0; r--) begin
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localparam g = 2**(LOGNUMWAYS-r-1);
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for(a = g-1; a > 0; a--) begin
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localparam t0 = s - 2**(g-1);
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localparam t1 = t0 - 1;
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s = s - 1;
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end
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end
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end
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-----/\----- EXCLUDED -----/\----- */
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/* -----\/----- EXCLUDED -----\/-----
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genvar row2;
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logic [LOGNUMWAYS-1:0] indices [LOGNUMWAYS-1:0];
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integer jindex;
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always_comb begin
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rawEn[LOGNUMWAYS-1] = 1;
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for(jindex = 0; jindex < LOGNUMWAYS-1; jindex++) begin
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rawEn[jindex] = 0;
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rawEn[jindex][~(HitWayEnc>>(jindex+1))] = 1;
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//cEn[2**(LOGNUMWAYS-jindex)-1+jindex:0] = rawEn[jindex][2**(LOGNUMWAYS-jindex)-1:0];
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end
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end
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-----/\----- EXCLUDED -----/\----- */
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// *** high priority to clean up
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/* -----\/----- EXCLUDED -----\/-----
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initial begin
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assert (NUMWAYS == 2 || NUMWAYS == 4) else $error("Only 2 or 4 ways supported");
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end
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-----/\----- EXCLUDED -----/\----- */
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// Replacement Bits: Register file
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// Needs to be resettable for simulation, but could omit reset for synthesis ***
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@ -47,7 +47,7 @@ module fctrl (
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output logic FRegWriteM, FRegWriteW, // FP register write enable
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output logic [2:0] FrmM, // FP rounding mode
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output logic [`FMTBITS-1:0] FmtE, FmtM, // FP format
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output logic DivStartE, // Start division or squareroot
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output logic FDivStartE, IDivStartE, // Start division or squareroot
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output logic XEnE, YEnE, ZEnE,
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output logic YEnForwardE, ZEnForwardE,
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output logic FWriteIntE, FCvtIntE, FWriteIntM, // Write to integer register
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@ -62,7 +62,7 @@ module fctrl (
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logic [`FCTRLW-1:0] ControlsD;
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logic IllegalFPUInstrD, IllegalFPUInstrE;
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logic FRegWriteD; // FP register write enable
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logic FDivStartD, FDivStartE, IDivStartE; // integer register write enable
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logic FDivStartD; // integer register write enable
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logic FWriteIntD; // integer register write enable
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logic FRegWriteE; // FP register write enable
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logic [2:0] OpCtrlD; // Select which opperation to do in each component
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@ -266,10 +266,8 @@ module fctrl (
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flopenrc #(15) DEAdrReg(clk, reset, FlushE, ~StallE, {InstrD[19:15], InstrD[24:20], InstrD[31:27]},
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{Adr1E, Adr2E, Adr3E});
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flopenrc #(1) DEFDivStartReg(clk, reset, FlushE, ~StallE|FDivBusyE, FDivStartD, FDivStartE);
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if (`M_SUPPORTED) begin
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assign IDivStartE = MDUE & Funct3E[2];
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assign DivStartE = FDivStartE | IDivStartE; // integer or floating-point division
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end else assign DivStartE = FDivStartE;
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if (`M_SUPPORTED) assign IDivStartE = MDUE & Funct3E[2];
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else assign IDivStartE = 0;
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assign FCvtIntE = (FResSelE == 2'b01);
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@ -40,7 +40,7 @@ module fdivsqrt(
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input logic XInfE, YInfE,
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input logic XZeroE, YZeroE,
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input logic XNaNE, YNaNE,
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input logic DivStartE,
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input logic FDivStartE, IDivStartE,
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input logic StallM,
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input logic StallE,
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input logic SqrtE, SqrtM,
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@ -48,7 +48,7 @@ module fdivsqrt(
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input logic [2:0] Funct3E, Funct3M,
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input logic MDUE, W64E,
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output logic DivSM,
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output logic DivBusy,
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output logic FDivBusyE,
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output logic DivDone,
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output logic [`NE+1:0] QeM,
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output logic [`DIVb:0] QmM
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@ -66,6 +66,7 @@ module fdivsqrt(
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logic SpecialCaseM;
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logic [`DIVBLEN:0] n, m;
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logic OTFCSwap, ALTB, BZero, As;
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logic DivStartE;
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fdivsqrtpreproc fdivsqrtpreproc(
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.clk, .DivStartE, .Xm(XmE), .QeM, .Xe(XeE), .Fmt(FmtE), .Ye(YeE),
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@ -74,14 +75,14 @@ module fdivsqrt(
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.ForwardedSrcAE, .ForwardedSrcBE, .Funct3E, .Funct3M, .MDUE, .W64E);
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fdivsqrtfsm fdivsqrtfsm(
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.clk, .reset, .FmtE, .XsE, .SqrtE,
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.DivBusy, .DivStartE,.StallE, .StallM, .DivDone, .XZeroE, .YZeroE,
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.FDivBusyE, .FDivStartE, .IDivStartE, .DivStartE, .StallE, .StallM, .DivDone, .XZeroE, .YZeroE,
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.XNaNE, .YNaNE, .MDUE, .n,
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.XInfE, .YInfE, .WZero, .SpecialCaseM);
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fdivsqrtiter fdivsqrtiter(
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.clk, .Firstun, .D, .FirstU, .FirstUM, .FirstC, .SqrtE, .SqrtM,
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.X,.Dpreproc, .FirstWS(WS), .FirstWC(WC),
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.DivStartE, .Xe(XeE), .Ye(YeE), .XZeroE, .YZeroE, .OTFCSwap,
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.DivBusy);
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.FDivBusyE);
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fdivsqrtpostproc fdivsqrtpostproc(
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.WS, .WC, .D, .FirstU, .FirstUM, .FirstC, .Firstun,
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.SqrtM, .SpecialCaseM, .RemOp(Funct3E[1]),
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@ -37,7 +37,7 @@ module fdivsqrtfsm(
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input logic XInfE, YInfE,
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input logic XZeroE, YZeroE,
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input logic XNaNE, YNaNE,
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input logic DivStartE,
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input logic FDivStartE, IDivStartE,
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input logic XsE,
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input logic SqrtE,
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input logic StallE,
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@ -45,8 +45,9 @@ module fdivsqrtfsm(
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input logic WZero,
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input logic MDUE,
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input logic [`DIVBLEN:0] n,
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output logic DivStartE,
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output logic DivDone,
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output logic DivBusy,
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output logic FDivBusyE,
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output logic SpecialCaseM
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);
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@ -57,6 +58,15 @@ module fdivsqrtfsm(
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logic [`DURLEN-1:0] cycles;
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logic SpecialCaseE;
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// *** start logic is presently in fctl. Make it look more like integer division start logic
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// DivStartE comes from fctrl, reflecitng the start of floating-point and possibly integer division
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assign DivStartE = (FDivStartE | IDivStartE) & (state == IDLE) & ~StallM;
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assign DivDone = (state == DONE) | (WZero & (state == BUSY)); // *** used in postprocess.sv and round.sv. This doesn't seem proper. They break when removed.
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assign FDivBusyE = (state == BUSY & ~DivDone); // *** want to add | DivStartE but it creates comb loop
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// Divider control signals from MDU
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//assign DivBusyE = (state == BUSY) | DivStartE;
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// terminate immediately on special cases
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assign SpecialCaseE = XZeroE | (YZeroE&~SqrtE) | XInfE | YInfE | XNaNE | YNaNE | (XsE&SqrtE);
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flopenr #(1) SpecialCaseReg(clk, reset, ~StallM, SpecialCaseE, SpecialCaseM); // save SpecialCase for checking in fdivsqrtpostproc
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@ -120,8 +130,5 @@ module fdivsqrtfsm(
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end
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end
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// *** start logic is presently in fctl. Make it look more like integer division start logic
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assign DivDone = (state == DONE) | (WZero & (state == BUSY));
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assign DivBusy = (state == BUSY & ~DivDone);
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endmodule
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@ -33,7 +33,7 @@
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module fdivsqrtiter(
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input logic clk,
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input logic DivStartE,
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input logic DivBusy,
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input logic FDivBusyE,
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input logic [`NE-1:0] Xe, Ye,
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input logic XZeroE, YZeroE,
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input logic SqrtE,
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@ -85,8 +85,8 @@ module fdivsqrtiter(
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// Residual WS/SC registers/initializaiton mux
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mux2 #(`DIVb+4) wsmux(WS[`DIVCOPIES], X, DivStartE, WSN);
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mux2 #(`DIVb+4) wcmux(WC[`DIVCOPIES], '0, DivStartE, WCN);
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flopen #(`DIVb+4) wsflop(clk, DivStartE|DivBusy, WSN, WS[0]);
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flopen #(`DIVb+4) wcflop(clk, DivStartE|DivBusy, WCN, WC[0]);
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flopen #(`DIVb+4) wsflop(clk, DivStartE|FDivBusyE, WSN, WS[0]);
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flopen #(`DIVb+4) wcflop(clk, DivStartE|FDivBusyE, WCN, WC[0]);
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// UOTFC Result U and UM registers/initialization mux
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// Initialize U to 1.0 and UM to 0 for square root; U to 0 and UM to -1 for division
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@ -94,8 +94,8 @@ module fdivsqrtiter(
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assign initUM = SqrtE ? 0 : {1'b1, {(`DIVb){1'b0}}};
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mux2 #(`DIVb+1) Umux(UNext[`DIVCOPIES-1], initU, DivStartE, UMux);
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mux2 #(`DIVb+1) UMmux(UMNext[`DIVCOPIES-1], initUM, DivStartE, UMMux);
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flopen #(`DIVb+1) UReg(clk, DivStartE|DivBusy, UMux, U[0]);
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flopen #(`DIVb+1) UMReg(clk, DivStartE|DivBusy, UMMux, UM[0]);
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flopen #(`DIVb+1) UReg(clk, DivStartE|FDivBusyE, UMux, U[0]);
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flopen #(`DIVb+1) UMReg(clk, DivStartE|FDivBusyE, UMMux, UM[0]);
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// C register/initialization mux
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// Initialize C to -1 for sqrt and -R for division
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@ -103,7 +103,7 @@ module fdivsqrtiter(
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assign initCUpper = SqrtE ? 2'b11 : (`RADIX == 4) ? 2'b00 : 2'b10;
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assign initC = {initCUpper, {`DIVb{1'b0}}};
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mux2 #(`DIVb+2) Cmux(C[`DIVCOPIES], initC, DivStartE, CMux);
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flopen #(`DIVb+2) cflop(clk, DivStartE|DivBusy, CMux, C[0]);
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flopen #(`DIVb+2) cflop(clk, DivStartE|FDivBusyE, CMux, C[0]);
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// Divisior register
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flopen #(`DIVN-1) dflop(clk, DivStartE, Dpreproc, D);
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@ -67,7 +67,7 @@ module fpu (
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logic FRegWriteW; // FP register write enable
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logic [2:0] FrmM; // FP rounding mode
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logic [`FMTBITS-1:0] FmtE, FmtM; // FP precision 0-single 1-double
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logic DivStartE; // Start division or squareroot
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logic FDivStartE, IDivStartE; // Start division or squareroot
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logic FWriteIntM; // Write to integer register
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logic [1:0] ForwardXE, ForwardYE, ForwardZE; // forwarding mux control signals
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logic [2:0] OpCtrlE, OpCtrlM; // Select which opperation to do in each component
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@ -167,7 +167,7 @@ module fpu (
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.Funct3E, .MDUE, .InstrD,
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.StallE, .StallM, .StallW, .FlushE, .FlushM, .FlushW, .FRM_REGW, .STATUS_FS, .FDivBusyE,
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.reset, .clk, .FRegWriteM, .FRegWriteW, .FrmM, .FmtE, .FmtM, .YEnForwardE, .ZEnForwardE,
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.DivStartE, .FWriteIntE, .FCvtIntE, .FWriteIntM, .OpCtrlE, .OpCtrlM, .IllegalFPUInstrM, .XEnE, .YEnE, .ZEnE,
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.FDivStartE, .IDivStartE, .FWriteIntE, .FCvtIntE, .FWriteIntM, .OpCtrlE, .OpCtrlM, .IllegalFPUInstrM, .XEnE, .YEnE, .ZEnE,
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.FResSelE, .FResSelM, .FResSelW, .PostProcSelE, .PostProcSelM, .FCvtIntW, .Adr1E, .Adr2E, .Adr3E);
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// FP register file
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@ -261,9 +261,9 @@ module fpu (
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// - fsqrt
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// *** add other opperations
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fdivsqrt fdivsqrt(.clk, .reset, .FmtE, .XmE, .YmE, .XeE, .YeE, .SqrtE(OpCtrlE[0]), .SqrtM(OpCtrlM[0]),
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.XInfE, .YInfE, .XZeroE, .YZeroE, .XNaNE, .YNaNE, .DivStartE(DivStartE), .XsE,
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.XInfE, .YInfE, .XZeroE, .YZeroE, .XNaNE, .YNaNE, .FDivStartE, .IDivStartE, .XsE,
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.ForwardedSrcAE, .ForwardedSrcBE, .Funct3E, .Funct3M, .MDUE, .W64E,
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.StallE, .StallM, .DivSM, .DivBusy(FDivBusyE), .QeM, //***change divbusyE to M signal
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.StallE, .StallM, .DivSM, .FDivBusyE, .QeM,
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.QmM, .DivDone(DivDoneM));
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//
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@ -129,7 +129,7 @@ module postprocess (
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assign Mult = OpCtrl[2]&~OpCtrl[1]&~OpCtrl[0];
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assign CvtOp = (PostProcSel == 2'b00);
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assign FmaOp = (PostProcSel == 2'b10);
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assign DivOp = (PostProcSel == 2'b01)&DivDone;
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assign DivOp = (PostProcSel == 2'b01) & DivDone;
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assign Sqrt = OpCtrl[0];
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// is there an input of infinity or NaN being used
|
||||
|
||||
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