Branch logic simplification and remove unused signals

pipelined/src/fpu/fpu.sv

@@ -38,7 +38,6 @@ module fpu (
    input  logic  [`FLEN-1:0] ReadDataW,  // Read data (from LSU)
    input  logic  [`XLEN-1:0] ForwardedSrcAE, ForwardedSrcBE, // Integer input (from IEU)
    input  logic 		        StallE, StallM, StallW, // stall signals (from HZU)
-   //input  logic              TrapM,
    input  logic 		        FlushE, FlushM, FlushW, // flush signals (from HZU)
    input  logic  [4:0] 	     RdE, RdM, RdW,   // which FP register to write to (from IEU)
    input  logic  [1:0]       STATUS_FS,  // Is floating-point enabled? (From privileged unit)
@@ -98,7 +97,6 @@ module fpu (
    logic [`NF:0] 	   XmM, YmM, ZmM;                // input's fraction - memory stage
    logic 		      XNaNE, YNaNE, ZNaNE;                // is the input a NaN - execute stage
    logic 		      XNaNM, YNaNM, ZNaNM;                // is the input a NaN - memory stage
-   logic 		      XNaNQ, YNaNQ;                       // is the input a NaN - divide
    logic 		      XSNaNE, YSNaNE, ZSNaNE;             // is the input a signaling NaN - execute stage
    logic 		      XSNaNM, YSNaNM, ZSNaNM;             // is the input a signaling NaN - memory stage
    logic 		      XSubnormE, ZSubnormE, ZSubnormM;       // is the input Subnormalized
@@ -128,9 +126,8 @@ module fpu (
    
    //divide signals
    logic [`DIVb:0]      QmM;
-   logic [`NE+1:0]      QeE, QeM; 
+   logic [`NE+1:0]      QeM; 
    logic                DivSM;
-//   logic                DivDoneM;
    logic                FDivDoneE, IFDivStartE;
 
    // result and flag signals

pipelined/src/fpu/unpackinput.sv

@@ -46,7 +46,6 @@ module unpackinput (
 );
  
     logic [`NF-1:0] Frac; //Fraction of XYZ
-    logic           ExpZero;
     logic           BadNaNBox;
     
     if (`FPSIZES == 1) begin        // if there is only one floating point format supported

pipelined/src/ieu/comparator.sv

@@ -105,7 +105,6 @@ endmodule
 
 
 module comparator2 #(parameter WIDTH=64) (
-  input  logic             clk, reset,
   input  logic [WIDTH-1:0] a, b,
   output logic [2:0]       flags);
 

pipelined/src/ieu/controller.sv

@@ -219,9 +219,11 @@ module controller(
                            {IEURegWriteE, ResultSrcE, MemRWE, JumpE, BranchE, ALUControlE, ALUSrcAE, ALUSrcBE, ALUResultSrcE, CSRReadE, CSRWriteE, PrivilegedE, Funct3E, W64E, MDUE, AtomicE, InvalidateICacheE, FlushDCacheE, FenceE, InstrValidE});
 
   // Branch Logic
+  //  The comparator handles both signed and unsigned branches using BranchSignedE
+  //  Hence, only eq and lt flags are needed
   assign BranchSignedE = ~(Funct3E[2:1] == 2'b11);
   assign {eqE, ltE} = FlagsE;
-  mux3 #(1) branchflagmux(eqE, 1'b0, ltE, Funct3E[2:1], BranchFlagE);
+  mux2 #(1) branchflagmux(eqE, ltE, Funct3E[2], BranchFlagE);
   assign BranchTakenE = BranchFlagE ^ Funct3E[0];
   assign PCSrcE = JumpE | BranchE & BranchTakenE;