forked from Github_Repos/cvw
added changes to stvec of reference signatures, modified some tests to copy over reference file instead of running on sail
This commit is contained in:
Daniel Torres
parent
5d7171f6f8
commit
2bbfd67082
@ -34,7 +34,7 @@
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string tvpaths[] = '{
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"../../addins/imperas-riscv-tests/work/",
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"../../tests/riscof/work/riscv-arch-test/",
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"../../tests/wally-riscv-arch-test/work/", //"../../tests/riscof/work/wally-riscv-arch-test/", //
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"../../tests/riscof/work/wally-riscv-arch-test/",
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"../../tests/imperas-riscv-tests/work/",
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"../../benchmarks/coremark/work/",
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"../../addins/embench-iot/"
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@ -93,24 +93,8 @@ string tvpaths[] = '{
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"bd_sizeopt_speed/src/wikisort/wikisort"
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};
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string wally64a[] = '{
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`WALLYTEST,
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"rv64i_m/privilege/WALLY-amo",
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"rv64i_m/privilege/WALLY-lrsc",
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"rv64i_m/privilege/WALLY-status-fp-enabled-01"
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};
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string wally32a[] = '{
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`WALLYTEST,
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"rv32i_m/privilege/WALLY-amo",
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"rv32i_m/privilege/WALLY-lrsc",
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"rv32i_m/privilege/WALLY-status-fp-enabled-01"
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};
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// *** restore CSR tests from Imperas old
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string extra64i[] = '{
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string extra64i[] = '{
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`MYIMPERASTEST,
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"rv64i_m/I/WALLY-ADD",
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"rv64i_m/I/WALLY-SUB",
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@ -920,6 +904,20 @@ string imperas32f[] = '{
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"rv32p/WALLY-CSR-PERMISSIONS-S"
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};
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string wally64a[] = '{
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`WALLYTEST,
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"rv64i_m/privilege/src/WALLY-amo.S",
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"rv64i_m/privilege/src/WALLY-lrsc.S",
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"rv64i_m/privilege/src/WALLY-status-fp-enabled-01.S"
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};
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string wally32a[] = '{
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`WALLYTEST,
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"rv32i_m/privilege/src/WALLY-amo.S",
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"rv32i_m/privilege/src/WALLY-lrsc.S",
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"rv32i_m/privilege/src/WALLY-status-fp-enabled-01.S"
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};
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string arch64priv[] = '{
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`RISCVARCHTEST,
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"rv64i_m/privilege/src/ebreak.S",
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@ -1492,212 +1490,126 @@ string imperas32f[] = '{
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string wally64i[] = '{
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`WALLYTEST,
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"rv64i_m/I/WALLY-ADD",
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"rv64i_m/I/WALLY-SLT",
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"rv64i_m/I/WALLY-SLTU",
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"rv64i_m/I/WALLY-SUB",
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"rv64i_m/I/WALLY-XOR"
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"rv64i_m/I/src/WALLY-ADD.S",
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"rv64i_m/I/src/WALLY-SLT.S",
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"rv64i_m/I/src/WALLY-SLTU.S",
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"rv64i_m/I/src/WALLY-SUB.S",
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"rv64i_m/I/src/WALLY-XOR.S"
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};
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string wally64priv[] = '{
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`WALLYTEST,
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"rv64i_m/privilege/WALLY-status-tw-01",
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"rv64i_m/privilege/WALLY-csr-permission-s-01",
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"rv64i_m/privilege/WALLY-csr-permission-u-01",
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"rv64i_m/privilege/WALLY-minfo-01",
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"rv64i_m/privilege/WALLY-misa-01",
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"rv64i_m/privilege/WALLY-mmu-sv39",
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"rv64i_m/privilege/WALLY-mmu-sv48",
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"rv64i_m/privilege/WALLY-pma",
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"rv64i_m/privilege/WALLY-pmp",
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"rv64i_m/privilege/WALLY-trap-01",
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"rv64i_m/privilege/WALLY-trap-s-01",
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"rv64i_m/privilege/WALLY-trap-u-01",
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"rv64i_m/privilege/WALLY-mie-01",
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"rv64i_m/privilege/WALLY-sie-01",
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"rv64i_m/privilege/WALLY-mtvec-01",
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"rv64i_m/privilege/WALLY-stvec-01",
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"rv64i_m/privilege/WALLY-status-mie-01",
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"rv64i_m/privilege/WALLY-status-sie-01",
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"rv64i_m/privilege/WALLY-trap-sret-01",
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"rv64i_m/privilege/WALLY-status-tw-01",
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"rv64i_m/privilege/WALLY-wfi-01"
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"rv64i_m/privilege/src/WALLY-csr-permission-s-01.S",
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"rv64i_m/privilege/src/WALLY-csr-permission-u-01.S",
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"rv64i_m/privilege/src/WALLY-mie-01.S",
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"rv64i_m/privilege/src/WALLY-minfo-01.S",
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"rv64i_m/privilege/src/WALLY-misa-01.S",
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"rv64i_m/privilege/src/WALLY-mmu-sv39.S",
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"rv64i_m/privilege/src/WALLY-mmu-sv48.S",
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"rv64i_m/privilege/src/WALLY-mtvec-01.S",
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"rv64i_m/privilege/src/WALLY-pma.S",
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"rv64i_m/privilege/src/WALLY-pmp.S",
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"rv64i_m/privilege/src/WALLY-sie-01.S",
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"rv64i_m/privilege/src/WALLY-status-mie-01.S",
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"rv64i_m/privilege/src/WALLY-status-sie-01.S",
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"rv64i_m/privilege/src/WALLY-status-tw-01.S",
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"rv64i_m/privilege/src/WALLY-stvec-01.S",
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"rv64i_m/privilege/src/WALLY-trap-01.S",
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"rv64i_m/privilege/src/WALLY-trap-s-01.S",
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"rv64i_m/privilege/src/WALLY-trap-sret-01.S",
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"rv64i_m/privilege/src/WALLY-trap-u-01.S",
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"rv64i_m/privilege/src/WALLY-wfi-01.S"
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};
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string wally64periph[] = '{
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`WALLYTEST,
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"rv64i_m/privilege/WALLY-periph"
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"rv64i_m/privilege/src/WALLY-periph.S"
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};
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string wally32e[] = '{
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`WALLYTEST,
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"rv32i_m/I/E-add-01",
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"rv32i_m/I/E-addi-01",
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"rv32i_m/I/E-and-01",
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"rv32i_m/I/E-andi-01",
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"rv32i_m/I/E-auipc-01",
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"rv32i_m/I/E-bge-01",
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"rv32i_m/I/E-bgeu-01",
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"rv32i_m/I/E-blt-01",
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"rv32i_m/I/E-bltu-01",
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"rv32i_m/I/E-bne-01",
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"rv32i_m/I/E-jal-01",
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"rv32i_m/I/E-jalr-01",
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"rv32i_m/I/E-lb-align-01",
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"rv32i_m/I/E-lbu-align-01",
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"rv32i_m/I/E-lh-align-01",
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"rv32i_m/I/E-lhu-align-01",
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"rv32i_m/I/E-lui-01",
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"rv32i_m/I/E-lw-align-01",
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"rv32i_m/I/E-or-01",
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"rv32i_m/I/E-ori-01",
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"rv32i_m/I/E-sb-align-01",
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"rv32i_m/I/E-sh-align-01",
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"rv32i_m/I/E-sll-01",
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"rv32i_m/I/E-slli-01",
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"rv32i_m/I/E-slt-01",
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"rv32i_m/I/E-slti-01",
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"rv32i_m/I/E-sltiu-01",
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"rv32i_m/I/E-sltu-01",
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"rv32i_m/I/E-sra-01",
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"rv32i_m/I/E-srai-01",
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"rv32i_m/I/E-srl-01",
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"rv32i_m/I/E-srli-01",
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"rv32i_m/I/E-sub-01",
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"rv32i_m/I/E-sw-align-01",
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"rv32i_m/I/E-xor-01",
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"rv32i_m/I/E-xori-01"
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"rv32i_m/I/src/E-add-01.S",
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"rv32i_m/I/src/E-addi-01.S",
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"rv32i_m/I/src/E-and-01.S",
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"rv32i_m/I/src/E-andi-01.S",
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"rv32i_m/I/src/E-auipc-01.S",
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"rv32i_m/I/src/E-bge-01.S",
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"rv32i_m/I/src/E-bgeu-01.S",
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"rv32i_m/I/src/E-blt-01.S",
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"rv32i_m/I/src/E-bltu-01.S",
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"rv32i_m/I/src/E-bne-01.S",
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"rv32i_m/I/src/E-jal-01.S",
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"rv32i_m/I/src/E-jalr-01.S",
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"rv32i_m/I/src/E-lb-align-01.S",
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"rv32i_m/I/src/E-lbu-align-01.S",
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"rv32i_m/I/src/E-lh-align-01.S",
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"rv32i_m/I/src/E-lhu-align-01.S",
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"rv32i_m/I/src/E-lui-01.S",
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"rv32i_m/I/src/E-lw-align-01.S",
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"rv32i_m/I/src/E-or-01.S",
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"rv32i_m/I/src/E-ori-01.S",
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"rv32i_m/I/src/E-sb-align-01.S",
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"rv32i_m/I/src/E-sh-align-01.S",
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"rv32i_m/I/src/E-sll-01.S",
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"rv32i_m/I/src/E-slli-01.S",
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"rv32i_m/I/src/E-slt-01.S",
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"rv32i_m/I/src/E-slti-01.S",
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"rv32i_m/I/src/E-sltiu-01.S",
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"rv32i_m/I/src/E-sltu-01.S",
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"rv32i_m/I/src/E-sra-01.S",
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"rv32i_m/I/src/E-srai-01.S",
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"rv32i_m/I/src/E-srl-01.S",
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"rv32i_m/I/src/E-srli-01.S",
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"rv32i_m/I/src/E-sub-01.S",
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"rv32i_m/I/src/E-sw-align-01.S",
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"rv32i_m/I/src/E-xor-01.S",
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"rv32i_m/I/src/E-xori-01.S"
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};
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string wally32i[] = '{
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string wally32i[] = '{
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`WALLYTEST,
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"rv32i_m/I/WALLY-ADD",
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"rv32i_m/I/WALLY-SLT",
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"rv32i_m/I/WALLY-SLTU",
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"rv32i_m/I/WALLY-SUB",
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"rv32i_m/I/WALLY-XOR"
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"rv32i_m/I/src/WALLY-ADD.S",
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"rv32i_m/I/src/WALLY-SLT.S",
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"rv32i_m/I/src/WALLY-SLTU.S",
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"rv32i_m/I/src/WALLY-SUB.S",
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"rv32i_m/I/src/WALLY-XOR.S"
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};
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string wally32priv[] = '{
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`WALLYTEST,
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"rv32i_m/privilege/WALLY-csr-permission-s-01",
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"rv32i_m/privilege/WALLY-csr-permission-u-01",
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"rv32i_m/privilege/WALLY-minfo-01",
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"rv32i_m/privilege/WALLY-misa-01",
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"rv32i_m/privilege/WALLY-mmu-sv32",
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"rv32i_m/privilege/WALLY-pma",
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"rv32i_m/privilege/WALLY-pmp",
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"rv32i_m/privilege/WALLY-trap-01",
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"rv32i_m/privilege/WALLY-trap-s-01",
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"rv32i_m/privilege/WALLY-trap-u-01",
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"rv32i_m/privilege/WALLY-mie-01",
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"rv32i_m/privilege/WALLY-sie-01",
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"rv32i_m/privilege/WALLY-mtvec-01",
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"rv32i_m/privilege/WALLY-stvec-01",
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"rv32i_m/privilege/WALLY-status-mie-01",
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"rv32i_m/privilege/WALLY-status-sie-01",
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"rv32i_m/privilege/WALLY-trap-sret-01",
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"rv32i_m/privilege/WALLY-status-tw-01",
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"rv32i_m/privilege/WALLY-wfi-01"
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"rv32i_m/privilege/src/WALLY-csr-permission-s-01.S",
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"rv32i_m/privilege/src/WALLY-csr-permission-u-01.S",
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"rv32i_m/privilege/src/WALLY-mie-01.S",
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"rv32i_m/privilege/src/WALLY-minfo-01.S",
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"rv32i_m/privilege/src/WALLY-misa-01.S",
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"rv32i_m/privilege/src/WALLY-mmu-sv32.S",
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"rv32i_m/privilege/src/WALLY-mtvec-01.S",
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"rv32i_m/privilege/src/WALLY-pma.S",
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"rv32i_m/privilege/src/WALLY-pmp.S",
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"rv32i_m/privilege/src/WALLY-sie-01.S",
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"rv32i_m/privilege/src/WALLY-status-mie-01.S",
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"rv32i_m/privilege/src/WALLY-status-sie-01.S",
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"rv32i_m/privilege/src/WALLY-status-tw-01.S",
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"rv32i_m/privilege/src/WALLY-stvec-01.S",
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"rv32i_m/privilege/src/WALLY-trap-01.S",
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"rv32i_m/privilege/src/WALLY-trap-s-01.S",
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"rv32i_m/privilege/src/WALLY-trap-sret-01.S",
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"rv32i_m/privilege/src/WALLY-trap-u-01.S",
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"rv32i_m/privilege/src/WALLY-wfi-01.S"
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};
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string wally32periph[] = '{
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`WALLYTEST,
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// "rv32i_m/privilege/WALLY-gpio-01",
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// "rv32i_m/privilege/WALLY-clint-01"
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"rv32i_m/privilege/WALLY-plic-01"
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// "rv32i_m/privilege/WALLY-uart-01"
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"rv32i_m/privilege/src/WALLY-gpio-01.S",
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"rv32i_m/privilege/src/WALLY-clint-01.S",
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"rv32i_m/privilege/src/WALLY-uart-01.S",
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"rv32i_m/privilege/src/WALLY-plic-01.S"
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};
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// riscof test paths, to replace existing paths once riscof flow is working
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// string wally64a[] = '{
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// `WALLYTEST,
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// "rv64i_m/privilege/src/WALLY-amo.S",
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// "rv64i_m/privilege/src/WALLY-lrsc.S",
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// "rv64i_m/privilege/src/WALLY-status-fp-enabled-01.S"
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// };
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// string wally32a[] = '{
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// `WALLYTEST,
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// "rv32i_m/privilege/src/WALLY-amo.S",
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// "rv32i_m/privilege/src/WALLY-lrsc.S",
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// "rv32i_m/privilege/src/WALLY-status-fp-enabled-01.S"
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// };
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// string wally64i[] = '{
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// `WALLYTEST,
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// "rv64i_m/I/src/WALLY-ADD.S",
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// "rv64i_m/I/src/WALLY-SLT.S",
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// "rv64i_m/I/src/WALLY-SLTU.S",
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// "rv64i_m/I/src/WALLY-SUB.S",
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// "rv64i_m/I/src/WALLY-XOR.S"
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// };
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// string wally64priv[] = '{
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// `WALLYTEST,
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// "rv64i_m/privilege/src/WALLY-csr-permission-s-01.S",
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// "rv64i_m/privilege/src/WALLY-csr-permission-u-01.S",
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// "rv64i_m/privilege/src/WALLY-mie-01.S",
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// "rv64i_m/privilege/src/WALLY-minfo-01.S",
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// "rv64i_m/privilege/src/WALLY-misa-01.S",
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// "rv64i_m/privilege/src/WALLY-mmu-sv39.S",
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// "rv64i_m/privilege/src/WALLY-mmu-sv48.S",
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// "rv64i_m/privilege/src/WALLY-mtvec-01.S",
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// "rv64i_m/privilege/src/WALLY-pma.S",
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// "rv64i_m/privilege/src/WALLY-pmp.S",
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// "rv64i_m/privilege/src/WALLY-sie-01.S",
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// "rv64i_m/privilege/src/WALLY-status-mie-01.S",
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// "rv64i_m/privilege/src/WALLY-status-sie-01.S",
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// "rv64i_m/privilege/src/WALLY-status-tw-01.S",
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// "rv64i_m/privilege/src/WALLY-stvec-01.S",
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// "rv64i_m/privilege/src/WALLY-trap-01.S",
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// "rv64i_m/privilege/src/WALLY-trap-s-01.S",
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// "rv64i_m/privilege/src/WALLY-trap-sret-01.S",
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// "rv64i_m/privilege/src/WALLY-trap-u-01.S",
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// "rv64i_m/privilege/src/WALLY-wfi-01.S"
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// };
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// string wally64periph[] = '{
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// `WALLYTEST,
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// "rv64i_m/privilege/src/WALLY-periph.S"
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// };
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string wally32d[] = '{
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`WALLYTEST,
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"rv32i_m/D/src/WALLY-fld.S"
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};
|
||||
|
||||
// string wally32i[] = '{
|
||||
// `WALLYTEST,
|
||||
// "rv32i_m/I/src/WALLY-ADD.S",
|
||||
// "rv32i_m/I/src/WALLY-SLT.S",
|
||||
// "rv32i_m/I/src/WALLY-SLTU.S",
|
||||
// "rv32i_m/I/src/WALLY-SUB.S",
|
||||
// "rv32i_m/I/src/WALLY-XOR.S"
|
||||
// };
|
||||
|
||||
// string wally32priv[] = '{
|
||||
// `WALLYTEST,
|
||||
// "rv32i_m/privilege/src/WALLY-csr-permission-s-01.S",
|
||||
// "rv32i_m/privilege/src/WALLY-csr-permission-u-01.S",
|
||||
// "rv32i_m/privilege/src/WALLY-mie-01.S",
|
||||
// "rv32i_m/privilege/src/WALLY-minfo-01.S",
|
||||
// "rv32i_m/privilege/src/WALLY-misa-01.S",
|
||||
// "rv32i_m/privilege/src/WALLY-mmu-sv32.S",
|
||||
// "rv32i_m/privilege/src/WALLY-mtvec-01.S",
|
||||
// "rv32i_m/privilege/src/WALLY-pma.S",
|
||||
// "rv32i_m/privilege/src/WALLY-pmp.S",
|
||||
// "rv32i_m/privilege/src/WALLY-sie-01.S",
|
||||
// "rv32i_m/privilege/src/WALLY-status-mie-01.S",
|
||||
// "rv32i_m/privilege/src/WALLY-status-sie-01.S",
|
||||
// "rv32i_m/privilege/src/WALLY-status-tw-01.S",
|
||||
// "rv32i_m/privilege/src/WALLY-stvec-01.S",
|
||||
// "rv32i_m/privilege/src/WALLY-trap-01.S",
|
||||
// "rv32i_m/privilege/src/WALLY-trap-s-01.S",
|
||||
// "rv32i_m/privilege/src/WALLY-trap-sret-01.S",
|
||||
// "rv32i_m/privilege/src/WALLY-trap-u-01.S",
|
||||
// "rv32i_m/privilege/src/WALLY-wfi-01.S"
|
||||
// };
|
||||
};
|
||||
@ -23,6 +23,9 @@
|
||||
|
||||
#include "WALLY-TEST-LIB-32.h"
|
||||
|
||||
RVTEST_ISA("RV32I")
|
||||
RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*I.*); def Drvtest_mtrap_routine=True;def TEST_CASE_1=True;def NO_SAIL=True;",plic)
|
||||
|
||||
INIT_TESTS
|
||||
|
||||
TRAP_HANDLER m
|
||||
|
||||
@ -23,6 +23,9 @@
|
||||
|
||||
#include "WALLY-TEST-LIB-32.h"
|
||||
|
||||
RVTEST_ISA("RV32I")
|
||||
RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*I.*); def Drvtest_mtrap_routine=True;def TEST_CASE_1=True;def NO_SAIL=True;",plic-s)
|
||||
|
||||
INIT_TESTS
|
||||
|
||||
TRAP_HANDLER m
|
||||
|
||||
@ -24,7 +24,7 @@
|
||||
#include "WALLY-TEST-LIB-32.h"
|
||||
|
||||
RVTEST_ISA("RV32I")
|
||||
RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*I.*); def Drvtest_mtrap_routine=True;def TEST_CASE_1=True;",pmp)
|
||||
RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*I.*); def Drvtest_mtrap_routine=True;def TEST_CASE_1=True;def NO_SAIL=True;",pmp)
|
||||
|
||||
INIT_TESTS
|
||||
|
||||
|
||||
@ -23,6 +23,9 @@
|
||||
|
||||
#include "WALLY-TEST-LIB-32.h"
|
||||
|
||||
RVTEST_ISA("RV32I")
|
||||
RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*I.*); def Drvtest_mtrap_routine=True;def TEST_CASE_1=True;def NO_SAIL=True;",uart)
|
||||
|
||||
INIT_TESTS
|
||||
|
||||
TRAP_HANDLER m
|
||||
|
||||
@ -14,13 +14,13 @@
|
||||
00000000
|
||||
00000003 # mcause from Breakpoint
|
||||
00000000
|
||||
80000400 # mtval of breakpoint instruction adress (0x80000400)
|
||||
800003f4 # mtval of breakpoint instruction adress (0x80000400)
|
||||
00000000
|
||||
00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0
|
||||
00000000
|
||||
00000004 # mcause from load address misaligned
|
||||
00000000
|
||||
80000409 # mtval of misaligned address (0x80000409)
|
||||
800003fd # mtval of misaligned address (0x80000409)
|
||||
00000000
|
||||
00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0
|
||||
00000000
|
||||
@ -32,7 +32,7 @@
|
||||
00000000
|
||||
00000006 # mcause from store misaligned
|
||||
00000000
|
||||
80000421 # mtval of address with misaligned store instr (0x80000421)
|
||||
80000415 # mtval of address with misaligned store instr (0x80000421)
|
||||
00000000
|
||||
00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0
|
||||
00000000
|
||||
@ -126,13 +126,13 @@ ffffffff
|
||||
00000000
|
||||
00000003 # mcause from Breakpoint
|
||||
00000000
|
||||
80000400 # mtval of breakpoint instruction adress (0x80000400)
|
||||
800003f4 # mtval of breakpoint instruction adress (0x80000400)
|
||||
00000000
|
||||
00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0
|
||||
00000000
|
||||
00000004 # mcause from load address misaligned
|
||||
00000000
|
||||
80000409 # mtval of misaligned address (0x80000409)
|
||||
800003fd # mtval of misaligned address (0x80000409)
|
||||
00000000
|
||||
00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0
|
||||
00000000
|
||||
@ -144,7 +144,7 @@ ffffffff
|
||||
00000000
|
||||
00000006 # mcause from store misaligned
|
||||
00000000
|
||||
80000421 # mtval of address with misaligned store instr (0x80000421)
|
||||
80000415 # mtval of address with misaligned store instr (0x80000421)
|
||||
00000000
|
||||
00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0
|
||||
00000000
|
||||
|
||||
@ -20,13 +20,13 @@
|
||||
00000000
|
||||
00000003 # scause from Breakpoint
|
||||
00000000
|
||||
80000400 # stval of breakpoint instruction adress (0x80000400)
|
||||
800003f4 # stval of breakpoint instruction adress (0x80000400)
|
||||
00000000
|
||||
00000800 # masked out mstatus.mpp = 1, mstatus.MPIE = 0, and mstatus.MIE = 0
|
||||
00000000
|
||||
00000004 # scause from load address misaligned
|
||||
00000000
|
||||
80000409 # stval of misaligned address (0x80000409)
|
||||
800003fd # stval of misaligned address (0x80000409)
|
||||
00000000
|
||||
00000800 # masked out mstatus.mpp = 1, mstatus.MPIE = 0, and mstatus.MIE = 0
|
||||
00000000
|
||||
@ -38,7 +38,7 @@
|
||||
00000000
|
||||
00000006 # scause from store misaligned
|
||||
00000000
|
||||
80000421 # stval of address with misaligned store instr (0x80000421)
|
||||
80000415 # stval of address with misaligned store instr (0x80000421)
|
||||
00000000
|
||||
00000800 # masked out mstatus.mpp = 1, mstatus.MPIE = 0, and mstatus.MIE = 0
|
||||
00000000
|
||||
@ -130,13 +130,13 @@ ffffffff
|
||||
00000000
|
||||
00000003 # scause from Breakpoint
|
||||
00000000
|
||||
80000400 # stval of breakpoint instruction adress (0x80000400)
|
||||
800003f4 # stval of breakpoint instruction adress (0x80000400)
|
||||
00000000
|
||||
00000120 # masked out sstatus.SPP = 1, sstatus.SPIE = 1, and sstatus.SIE = 0
|
||||
00000000
|
||||
00000004 # scause from load address misaligned
|
||||
00000000
|
||||
80000409 # stval of misaligned address (0x80000409)
|
||||
800003fd # stval of misaligned address (0x80000409)
|
||||
00000000
|
||||
00000120 # masked out sstatus.SPP = 1, sstatus.SPIE = 1, and sstatus.SIE = 0
|
||||
00000000
|
||||
@ -148,7 +148,7 @@ ffffffff
|
||||
00000000
|
||||
00000006 # scause from store misaligned
|
||||
00000000
|
||||
80000421 # stval of address with misaligned store instr (0x80000421)
|
||||
80000415 # stval of address with misaligned store instr (0x80000421)
|
||||
00000000
|
||||
00000120 # masked out sstatus.SPP = 1, sstatus.SPIE = 1, and sstatus.SIE = 0
|
||||
00000000
|
||||
|
||||
@ -20,13 +20,13 @@
|
||||
00000000
|
||||
00000003 # scause from Breakpoint
|
||||
00000000
|
||||
80000400 # stval of breakpoint instruction adress (0x80000400)
|
||||
800003f4 # stval of breakpoint instruction adress (0x80000400)
|
||||
00000000
|
||||
00000000 # masked out mstatus.mpp = 0, mstatus.MPIE = 0, and mstatus.MIE = 0
|
||||
00000000
|
||||
00000004 # scause from load address misaligned
|
||||
00000000
|
||||
80000409 # stval of misaligned address (0x80000409)
|
||||
800003fd # stval of misaligned address (0x80000409)
|
||||
00000000
|
||||
00000000 # masked out mstatus.mpp = 0, mstatus.MPIE = 0, and mstatus.MIE = 0
|
||||
00000000
|
||||
@ -38,7 +38,7 @@
|
||||
00000000
|
||||
00000006 # scause from store misaligned
|
||||
00000000
|
||||
80000421 # stval of address with misaligned store instr (0x80000421)
|
||||
80000415 # stval of address with misaligned store instr (0x80000421)
|
||||
00000000
|
||||
00000000 # masked out mstatus.mpp = 0, mstatus.MPIE = 0, and mstatus.MIE = 0
|
||||
00000000
|
||||
@ -116,13 +116,13 @@ ffffffff
|
||||
00000000
|
||||
00000003 # scause from Breakpoint
|
||||
00000000
|
||||
80000400 # stval of breakpoint instruction adress (0x80000400)
|
||||
800003f4 # stval of breakpoint instruction adress (0x80000400)
|
||||
00000000
|
||||
00000020 # masked out sstatus.SPP = 0, sstatus.SPIE = 1, and sstatus.SIE = 0
|
||||
00000000
|
||||
00000004 # scause from load address misaligned
|
||||
00000000
|
||||
80000409 # stval of misaligned address (0x80000409)
|
||||
800003fd # stval of misaligned address (0x80000409)
|
||||
00000000
|
||||
00000020 # masked out sstatus.SPP = 0, sstatus.SPIE = 1, and sstatus.SIE = 0
|
||||
00000000
|
||||
@ -134,7 +134,7 @@ ffffffff
|
||||
00000000
|
||||
00000006 # scause from store misaligned
|
||||
00000000
|
||||
80000421 # stval of address with misaligned store instr (0x80000421)
|
||||
80000415 # stval of address with misaligned store instr (0x80000421)
|
||||
00000000
|
||||
00000020 # masked out sstatus.SPP = 0, sstatus.SPIE = 1, and sstatus.SIE = 0
|
||||
00000000
|
||||
|
||||
@ -23,7 +23,7 @@
|
||||
|
||||
#include "WALLY-TEST-LIB-64.h"
|
||||
RVTEST_ISA("RV64I")
|
||||
RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*);def TEST_CASE_1=True;",pmp)
|
||||
RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*);def TEST_CASE_1=True;def NO_SAIL=True;",pmp)
|
||||
|
||||
INIT_TESTS
|
||||
|
||||
|
||||
@ -23,7 +23,7 @@
|
||||
|
||||
#include "WALLY-TEST-LIB-64.h"
|
||||
RVTEST_ISA("RV64I")
|
||||
RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*);def TEST_CASE_1=True;",status-sie)
|
||||
RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*);def TEST_CASE_1=True;def NO_SAIL=True;",status-sie)
|
||||
|
||||
INIT_TESTS
|
||||
|
||||
|
||||
@ -24,7 +24,7 @@
|
||||
|
||||
#include "WALLY-TEST-LIB-64.h"
|
||||
RVTEST_ISA("RV64I")
|
||||
RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*);def TEST_CASE_1=True;",status-tw)
|
||||
RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*);def TEST_CASE_1=True;def NO_SAIL=True;",status-tw)
|
||||
|
||||
INIT_TESTS
|
||||
|
||||
|
||||
Loading…
Reference in New Issue
Block a user