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Removed the old two port ram and replaced it with the fixed version.

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The fixed version is renamed to ram2p1r1wb.sv
This commit is contained in:
Ross Thompson 2023-01-24 17:22:00 -06:00
parent 1170dc7250
commit 1acbdaeca6
10 changed files with 11 additions and 99 deletions
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88
pipelined/src/generic/mem/ram2p1r1wb.sv
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@ -1,88 +0,0 @@
///////////////////////////////////////////
// ram2p1r1wb
//
// Written: Ross Thomposn
// Email: ross1728@gmail.com
// Created: February 14, 2021
// Modified:
//
// Purpose: Behavioral model of two port SRAM. While this is synthesizable it will produce a flip flop based memory which
// behaves with the timing of an SRAM typical of GF 14nm, 32nm, and 45nm.
//
//
// to preload this memory we can use the following command
// in modelsim's do file.
// mem load -infile <relative path to the text file > -format <bin|hex> <hierarchy to the memory.>
// example
// mem load -infile twoBitPredictor.txt -format bin testbench/dut/core/ifu/bpred/DirPredictor/memory/memory
//
// A component of the CORE-V-WALLY configurable RISC-V project.
//
// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
//
// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
//
// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
// except in compliance with the License, or, at your option, the Apache License version 2.0. You
// may obtain a copy of the License at
//
// https://solderpad.org/licenses/SHL-2.1/
//
// Unless required by applicable law or agreed to in writing, any work distributed under the
// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
// either express or implied. See the License for the specific language governing permissions
// and limitations under the License.
////////////////////////////////////////////////////////////////////////////////////////////////
`include "wally-config.vh"
module ram2p1r1wb #(parameter DEPTH = 10, WIDTH = 2) (
input logic clk,
input logic reset,
// port 1 is read only
input logic [DEPTH-1:0] ra1,
output logic [WIDTH-1:0] rd1,
input logic ren1,
// port 2 is write only
input logic [DEPTH-1:0] wa2,
input logic [WIDTH-1:0] wd2,
input logic wen2,
input logic [WIDTH-1:0] bwe2
);
logic [DEPTH-1:0] ra1q, wa2q;
logic wen2q;
logic [WIDTH-1:0] wd2q;
logic [WIDTH-1:0] mem[2**DEPTH-1:0];
logic [WIDTH-1:0] bwe;
// SRAMs address busses are always registered first
// *** likely issued DH and RT 12/20/22
// wrong enable for write port registers
// prefer to code read like ram1p1rw
// prefer not to have two-cycle write latency
// will require branch predictor changes
flopenr #(DEPTH) ra1Reg(clk, reset, ren1, ra1, ra1q);
flopenr #(DEPTH) wa2Reg(clk, reset, ren1, wa2, wa2q);
flopr #(1) wen2Reg(clk, reset, wen2, wen2q);
flopenr #(WIDTH) wd2Reg(clk, reset, ren1, wd2, wd2q);
// read port
//assign rd1 = mem[ra1q];
always_ff @(posedge clk)
if(ren1) rd1 <= mem[ra1];
// write port
assign bwe = {WIDTH{wen2}} & bwe2;
always_ff @(posedge clk)
mem[wa2] <= wd2 & bwe | mem[wa2] & ~bwe;
endmodule

6
pipelined/src/generic/mem/ram2p1rwbefix.sv
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@ -1,8 +1,8 @@
///////////////////////////////////////////
// 1 port sram.
// 2 port sram.
//
// Written: ross1728@gmail.com May 3, 2021
// Basic sram with 1 read write port.
// Two port SRAM 1 read port and 1 write port.
// When clk rises Addr and LineWriteData are sampled.
// Following the clk edge read data is output from the sampled Addr.
// Write
@ -31,7 +31,7 @@
`include "wally-config.vh"
module ram2p1r1wbefix #(parameter DEPTH=128, WIDTH=256) (
module ram2p1r1wbe #(parameter DEPTH=128, WIDTH=256) (
input logic clk,
input logic ce1, ce2,
input logic [$clog2(DEPTH)-1:0] ra1,

2
pipelined/src/ifu/brpred/btb.sv
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@ -103,7 +103,7 @@ module btb
// *** optimize for byte write enables
ram2p1r1wbefix #(2**Depth, `XLEN+4) memory(
ram2p1r1wbe #(2**Depth, `XLEN+4) memory(
.clk, .ce1(~StallF | reset), .ra1(PCNextFIndex), .rd1({InstrClass, BTBPredPCF}),
.ce2(~StallE), .wa2(PCEIndex), .wd2({InstrClassE, IEUAdrE}), .we2(UpdateEN), .bwe2('1));

2
pipelined/src/ifu/brpred/foldedgshare.sv
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@ -77,7 +77,7 @@ module foldedgshare
assign FinalIndexNextF = IndexNextF[depth-1:0] ^ {{delta{1'b0}} , IndexNextF[k-1:depth]};
assign FinalIndexW = IndexW[depth-1:0] ^ {{delta{1'b0}} , IndexW[k-1:depth]};
ram2p1r1wbefix #(2**depth, 2) PHT(.clk(clk),
ram2p1r1wbe #(2**depth, 2) PHT(.clk(clk),
.ce1(~StallF | reset), .ce2(~StallW & ~FlushW),
.ra1(FinalIndexNextF),
.rd1(TableDirPredictionF),

2
pipelined/src/ifu/brpred/globalhistory.sv
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@ -51,7 +51,7 @@ module globalhistory
logic PCSrcM;
ram2p1r1wbefix #(2**k, 2) PHT(.clk(clk),
ram2p1r1wbe #(2**k, 2) PHT(.clk(clk),
.ce1(~StallF), .ce2(~StallM & ~FlushM),
.ra1(GHR),
.rd1(DirPredictionF),

2
pipelined/src/ifu/brpred/gshare.sv
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@ -54,7 +54,7 @@ module gshare
assign IndexNextF = GHR & {PCNextF[k+1] ^ PCNextF[1], PCNextF[k:2]};
assign IndexM = GHRM & {PCM[k+1] ^ PCM[1], PCM[k:2]};
ram2p1r1wbefix #(2**k, 2) PHT(.clk(clk),
ram2p1r1wbe #(2**k, 2) PHT(.clk(clk),
.ce1(~StallF), .ce2(~StallM & ~FlushM),
.ra1(IndexNextF),
.rd1(DirPredictionF),

2
pipelined/src/ifu/brpred/optgshare.sv
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@ -153,7 +153,7 @@ module optgshare
assign IndexM = GHRM[k-1:0] ^ {PCM[k+1] ^ PCM[1], PCM[k:2]};
assign IndexW = GHRW[k-1:0] ^ {PCW[k+1] ^ PCW[1], PCW[k:2]};
ram2p1r1wbefix #(2**k, 2) PHT(.clk(clk),
ram2p1r1wbe #(2**k, 2) PHT(.clk(clk),
.ce1(~StallF | reset), .ce2(~StallW & ~FlushW),
.ra1(IndexNextF),
.rd1(TableDirPredictionF),

2
pipelined/src/ifu/brpred/speculativeglobalhistory.sv
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@ -60,7 +60,7 @@ module speculativeglobalhistory
logic [1:0] ForwardNewDirPrediction, ForwardDirPredictionF;
ram2p1r1wbefix #(2**k, 2) PHT(.clk(clk),
ram2p1r1wbe #(2**k, 2) PHT(.clk(clk),
.ce1(~StallF | reset), .ce2(~StallW & ~FlushW),
.ra1(GHRNextF),
.rd1(TableDirPredictionF),

2
pipelined/src/ifu/brpred/speculativegshare.sv
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@ -70,7 +70,7 @@ module speculativegshare
assign IndexE = GHRE[k-1:0] ^ {PCE[k+1] ^ PCE[1], PCE[k:2]};
assign IndexM = GHRM[k-1:0] ^ {PCM[k+1] ^ PCM[1], PCM[k:2]};
ram2p1r1wbefix #(2**k, 2) PHT(.clk(clk),
ram2p1r1wbe #(2**k, 2) PHT(.clk(clk),
.ce1(~StallF | reset), .ce2(~StallW & ~FlushW),
.ra1(IndexNextF),
.rd1(TableDirPredictionF),

2
pipelined/src/ifu/brpred/twoBitPredictor.sv
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@ -56,7 +56,7 @@ module twoBitPredictor
assign IndexM = {PCM[k+1] ^ PCM[1], PCM[k:2]};
ram2p1r1wbefix #(2**k, 2) PHT(.clk(clk),
ram2p1r1wbe #(2**k, 2) PHT(.clk(clk),
.ce1(~StallF), .ce2(~StallM & ~FlushM),
.ra1(IndexNextF),
.rd1(DirPredictionF),