forked from Github_Repos/cvw
Radix 4 sqrt passing first two tests
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// fdivsqrt.sv
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//
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// Written: David_Harris@hmc.edu, me@KatherineParry.com, Cedar Turek
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// Written: David_Harris@hmc.edu, me@KatherineParry.com, cturek@hmc.edu
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// Modified:13 January 2022
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//
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// Purpose: Combined Divide and Square Root Floating Point and Integer Unit
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///////////////////////////////////////////
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// fdivsqrtfsm.sv
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//
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// Written: David_Harris@hmc.edu, me@KatherineParry.com, Cedar Turek
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// Written: David_Harris@hmc.edu, me@KatherineParry.com, cturek@hmc.edu
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// Modified:13 January 2022
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//
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// Purpose: Combined Divide and Square Root Floating Point and Integer Unit
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///////////////////////////////////////////
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// fdivsqrtpostproc.sv
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//
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// Written: David_Harris@hmc.edu, me@KatherineParry.com, Cedar Turek
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// Written: David_Harris@hmc.edu, me@KatherineParry.com, cturek@hmc.edu
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// Modified:13 January 2022
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//
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// Purpose: Combined Divide and Square Root Floating Point and Integer Unit
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@ -71,6 +71,6 @@ module fdivsqrtpostproc(
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// division takes the result from the next cycle, which is shifted to the left one more time so the square root also needs to be shifted
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always_comb
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if(NegSticky) QmM = FirstUM[`DIVb-(`RADIX/4):0] << SqrtM;
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else QmM = FirstU[`DIVb-(`RADIX/4):0] << SqrtM;
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if(NegSticky) QmM = FirstUM[`DIVb:(`RADIX/4)] << SqrtM;
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else QmM = FirstU[`DIVb:(`RADIX/4)] << SqrtM;
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endmodule
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///////////////////////////////////////////
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// fdivsqrtpreproc.sv
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//
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// Written: David_Harris@hmc.edu, me@KatherineParry.com, Cedar Turek
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// Written: David_Harris@hmc.edu, me@KatherineParry.com, cturek@hmc.edu
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// Modified:13 January 2022
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//
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// Purpose: Combined Divide and Square Root Floating Point and Integer Unit
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