forked from Github_Repos/cvw
More progress.
This commit is contained in:
Ross Thompson
parent
a532eb61ba
commit
63a824cca1
@ -169,11 +169,33 @@ add wave -noupdate -group Forward -color Thistle /testbench/dut/core/ieu/fw/Load
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add wave -noupdate -group {alu execution stage} /testbench/dut/core/ieu/dp/ALUResultE
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add wave -noupdate -group {alu execution stage} /testbench/dut/core/ieu/dp/SrcAE
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add wave -noupdate -group {alu execution stage} /testbench/dut/core/ieu/dp/SrcBE
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add wave -noupdate -expand -group AHB -expand -group multimanager -color Gold /testbench/dut/core/ebu/ebu/BusState
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add wave -noupdate -expand -group AHB -expand -group multimanager /testbench/dut/core/ebu/ebu/both
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add wave -noupdate -expand -group AHB -expand -group multimanager /testbench/dut/core/ebu/ebu/save
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add wave -noupdate -expand -group AHB -expand -group multimanager /testbench/dut/core/ebu/ebu/restore
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add wave -noupdate -expand -group AHB -expand -group multimanager /testbench/dut/core/ebu/ebu/dis
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add wave -noupdate -expand -group AHB -expand -group multimanager /testbench/dut/core/ebu/ebu/sel
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add wave -noupdate -expand -group AHB -expand -group multimanager /testbench/dut/core/ebu/ebu/IFUActive
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add wave -noupdate -expand -group AHB -expand -group multimanager /testbench/dut/core/ebu/ebu/LSUActive
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add wave -noupdate -expand -group AHB /testbench/dut/core/ebu/ebu/HTRANS
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add wave -noupdate -expand -group AHB /testbench/dut/core/ebu/ebu/Threshold
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add wave -noupdate -expand -group AHB /testbench/dut/core/ebu/ebu/HBURST
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add wave -noupdate -expand -group AHB /testbench/dut/core/ebu/ebu/HBURSTD
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add wave -noupdate -expand -group AHB -expand -group IFU /testbench/dut/core/ebu/ebu/IFUHTRANS
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add wave -noupdate -expand -group AHB -expand -group IFU /testbench/dut/core/ebu/ebu/IFUHADDR
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add wave -noupdate -expand -group AHB -expand -group IFU /testbench/dut/core/ebu/ebu/IFUHBURST
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add wave -noupdate -expand -group AHB -expand -group IFU /testbench/dut/core/ebu/ebu/IFUHREADY
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add wave -noupdate -expand -group AHB -expand -group LSU /testbench/dut/core/ebu/ebu/LSUReq
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add wave -noupdate -expand -group AHB -expand -group LSU /testbench/dut/core/ebu/ebu/LSUHTRANS
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add wave -noupdate -expand -group AHB -expand -group LSU /testbench/dut/core/ebu/ebu/LSUHSIZE
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add wave -noupdate -expand -group AHB -expand -group LSU /testbench/dut/core/ebu/ebu/LSUHBURST
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add wave -noupdate -expand -group AHB -expand -group LSU /testbench/dut/core/ebu/ebu/LSUHADDR
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add wave -noupdate -expand -group AHB -expand -group LSU /testbench/dut/core/HRDATA
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add wave -noupdate -expand -group AHB -expand -group LSU /testbench/dut/core/ebu/ebu/LSUHWRITE
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add wave -noupdate -expand -group AHB -expand -group LSU /testbench/dut/core/ebu/ebu/LSUHWSTRB
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add wave -noupdate -expand -group AHB -expand -group LSU /testbench/dut/core/ebu/ebu/LSUHWDATA
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add wave -noupdate -expand -group AHB -expand -group LSU /testbench/dut/core/ebu/ebu/LSUHREADY
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add wave -noupdate -expand -group AHB -expand -group LSU -color Pink /testbench/dut/core/lsu/LSUHREADY
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add wave -noupdate -expand -group AHB /testbench/dut/core/ebu/ebu/NextBusState
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add wave -noupdate -expand -group AHB /testbench/dut/core/ebu/ebu/HCLK
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add wave -noupdate -expand -group AHB /testbench/dut/core/ebu/ebu/HRESETn
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@ -196,11 +218,16 @@ add wave -noupdate -expand -group lsu /testbench/dut/core/lsu/LSUStallM
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add wave -noupdate -expand -group lsu /testbench/dut/core/lsu/ReadDataWordMuxM
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add wave -noupdate -expand -group lsu /testbench/dut/core/lsu/ReadDataM
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add wave -noupdate -expand -group lsu /testbench/dut/core/lsu/WriteDataM
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add wave -noupdate -expand -group lsu -expand -group bus /testbench/dut/core/ebu/ebu/HCLK
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add wave -noupdate -expand -group lsu -expand -group bus -color Gold /testbench/dut/core/lsu/bus/dcache/cachedp/AHBBuscachefsm/BusCurrState
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add wave -noupdate -expand -group lsu -expand -group bus /testbench/dut/core/lsu/bus/dcache/cachedp/AHBBuscachefsm/RW
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add wave -noupdate -expand -group lsu -expand -group bus /testbench/dut/core/lsu/bus/dcache/cachedp/AHBBuscachefsm/CacheRW
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add wave -noupdate -expand -group lsu -expand -group bus /testbench/dut/core/lsu/bus/dcache/cachedp/AHBBuscachefsm/Cacheable
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add wave -noupdate -expand -group lsu -expand -group bus /testbench/dut/core/lsu/BusStall
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add wave -noupdate -expand -group lsu -expand -group bus /testbench/dut/core/lsu/bus/dcache/cachedp/HTRANS
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add wave -noupdate -expand -group lsu -expand -group bus /testbench/dut/core/lsu/bus/dcache/cachedp/FetchBuffer
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add wave -noupdate -expand -group lsu -expand -group bus /testbench/dut/core/lsu/bus/dcache/cachedp/HRDATA
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add wave -noupdate -expand -group lsu /testbench/dut/core/lsu/bus/dcache/cachedp/WordCount
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add wave -noupdate -expand -group lsu -expand -group dcache -color Gold /testbench/dut/core/lsu/bus/dcache/dcache/cachefsm/CurrState
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add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/HitWay
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add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/SetValid
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@ -305,6 +332,7 @@ add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU
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add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/core/lsu/bus/dcache/dcache/FlushCache
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add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/core/lsu/bus/dcache/dcache/CacheStall
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add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/core/lsu/ReadDataWordM
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add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/core/lsu/bus/dcache/dcache/FinalWriteData
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add wave -noupdate -expand -group lsu -expand -group dcache -group status /testbench/dut/core/lsu/bus/dcache/dcache/HitWay
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add wave -noupdate -expand -group lsu -expand -group dcache -group status -color {Medium Orchid} /testbench/dut/core/lsu/bus/dcache/dcache/CacheHit
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add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/core/lsu/bus/dcache/dcache/CacheFetchLine
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@ -513,8 +541,8 @@ add wave -noupdate -group {ifu } /testbench/dut/core/ifu/bus/icache/cachedp/HTRA
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add wave -noupdate -group {ifu } /testbench/dut/core/ifu/bus/icache/cachedp/AHBBuscachefsm/CacheBusAck
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add wave -noupdate /testbench/dut/core/ifu/bus/icache/cachedp/AHBBuscachefsm/WordCountFlag
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TreeUpdate [SetDefaultTree]
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WaveRestoreCursors {{Cursor 2} {989221 ns} 1} {{Cursor 3} {999815 ns} 1} {{Cursor 4} {2306 ns} 0}
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quietly wave cursor active 3
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WaveRestoreCursors {{Cursor 2} {27610 ns} 0} {{Cursor 3} {334914 ns} 1} {{Cursor 4} {335206 ns} 1}
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quietly wave cursor active 1
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configure wave -namecolwidth 250
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configure wave -valuecolwidth 314
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configure wave -justifyvalue left
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@ -529,4 +557,4 @@ configure wave -griddelta 40
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configure wave -timeline 0
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configure wave -timelineunits ns
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update
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WaveRestoreZoom {2137 ns} {2477 ns}
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WaveRestoreZoom {27292 ns} {27764 ns}
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2
pipelined/src/cache/AHBBuscachefsm.sv
vendored
2
pipelined/src/cache/AHBBuscachefsm.sv
vendored
@ -131,7 +131,7 @@ module AHBBuscachefsm #(parameter integer WordCountThreshold,
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assign HTRANS = (BusCurrState == STATE_READY & HREADY & (|RW | |CacheRW)) |
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(BusCurrState == STATE_CAPTURE & ~HREADY) |
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(BusCurrState == STATE_CACHE_ACCESS & ~HREADY & |WordCount) ? AHB_NONSEQ :
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(BusCurrState == STATE_CACHE_ACCESS) ? AHB_SEQ : AHB_IDLE;
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(BusCurrState == STATE_CACHE_ACCESS & |WordCount) ? AHB_SEQ : AHB_IDLE;
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assign HWRITE = (BusCurrState == STATE_READY & (RW[0] | CacheRW[0])) | // *** might not be necessary, maybe just RW[0]
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(BusCurrState == STATE_CACHE_ACCESS & CacheRW[0]);
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@ -93,7 +93,13 @@ module ahbmultimanager
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logic IFUReq, LSUReq;
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logic IFUActive, LSUActive;
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logic WordCntEn;
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logic [4-1:0] NextWordCount, WordCount, WordCountDelayed;
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logic WordCountFlag;
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logic [2:0] LocalBurstType;
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logic CntReset;
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logic [3:0] Threshold;
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assign HCLK = clk;
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assign HRESETn = ~reset;
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@ -149,7 +155,7 @@ module ahbmultimanager
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assign save[1] = 1'b0;
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assign restore[1] = 1'b0;
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assign dis[1] = 1'b0;
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assign sel[1] = NextBusState == ARBITRATE ? LSUReq : 1'b0;
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assign sel[1] = NextBusState == ARBITRATE ? 1'b1: LSUReq;
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@ -163,7 +169,7 @@ module ahbmultimanager
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case (BusState)
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IDLE: if (both) NextBusState = ARBITRATE;
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else NextBusState = IDLE;
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ARBITRATE: if (HREADY)NextBusState = IDLE;
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ARBITRATE: if (HREADY & WordCountFlag) NextBusState = IDLE;
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else NextBusState = ARBITRATE;
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default: NextBusState = IDLE;
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endcase // case (BusState)
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@ -173,5 +179,39 @@ module ahbmultimanager
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assign HWDATA = LSUHWDATA;
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assign HWSTRB = LSUHWSTRB;
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flopenr #(4)
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WordCountReg(.clk(HCLK),
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.reset(~HRESETn | CntReset),
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.en(WordCntEn),
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.d(NextWordCount),
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.q(WordCount));
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// Used to store data from data phase of AHB.
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flopenr #(4)
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WordCountDelayedReg(.clk(HCLK),
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.reset(~HRESETn | CntReset),
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.en(WordCntEn),
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.d(WordCount),
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.q(WordCountDelayed));
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assign NextWordCount = WordCount + 1'b1;
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assign CntReset = NextBusState == IDLE;
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assign WordCountFlag = (WordCountDelayed == Threshold); // Detect when we are waiting on the final access.
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assign WordCntEn = (NextBusState == ARBITRATE & HREADY);
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logic [2:0] HBURSTD;
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flopenr #(3) HBURSTReg(.clk(HCLK), .reset(~HRESETn), .en(HTRANS == 2'b10), .d(HBURST), .q(HBURSTD));
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always_comb begin
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case(HBURSTD)
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0: Threshold = 4'b0000;
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3: Threshold = 4'b0011; // INCR4
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5: Threshold = 4'b0111; // INCR8
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7: Threshold = 4'b1111; // INCR16
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default: Threshold = 4'b0000; // INCR without end.
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endcase
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end
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endmodule
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@ -246,6 +246,8 @@ module lsu (
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logic [LOGBWPL-1:0] WordCount;
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logic SelUncachedAdr, DCacheBusAck;
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logic SelBusWord;
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logic [`XLEN-1:0] LSUHWDATA_noDELAY; //*** change name
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logic [`XLEN/8-1:0] ByteMaskMDelay;
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cache #(.LINELEN(`DCACHE_LINELENINBITS), .NUMLINES(`DCACHE_WAYSIZEINBYTES*8/LINELEN),
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.NUMWAYS(`DCACHE_NUMWAYS), .LOGBWPL(LOGBWPL), .WORDLEN(`LLEN), .MUXINTERVAL(`XLEN), .DCACHE(1)) dcache(
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@ -268,10 +270,15 @@ module lsu (
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.SelUncachedAdr, .RW(LSURWM & ~{IgnoreRequest, IgnoreRequest} & ~{CacheableM, CacheableM}), .CPUBusy, .Cacheable(CacheableM),
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.BusStall, .BusCommitted(BusCommittedM));
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mux2 #(`LLEN) UnCachedDataMux(.d0(LittleEndianReadDataWordM), .d1({{`LLEN-`XLEN{1'b0}}, FetchBuffer[`XLEN-1:0]}),
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mux2 #(`LLEN) UnCachedDataMux(.d0(LittleEndianReadDataWordM), .d1({{`LLEN-`XLEN{1'b0}}, FetchBuffer[`XLEN-1:0] }),
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.s(SelUncachedAdr), .y(ReadDataWordMuxM));
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mux2 #(`XLEN) LSUHWDATAMux(.d0(ReadDataWordM[`XLEN-1:0]), .d1(LSUWriteDataM[`XLEN-1:0]),
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.s(SelUncachedAdr), .y(LSUHWDATA));
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.s(SelUncachedAdr), .y(LSUHWDATA_noDELAY));
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flop #(`XLEN) wdreg(clk, LSUHWDATA_noDELAY, LSUHWDATA); // delay HWDATA by 1 cycle per spec; *** assumes AHBW = XLEN
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flop #(`XLEN/8) HWSTRBReg(clk, ByteMaskM[`XLEN/8-1:0], LSUHWSTRB);
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end else begin : passthrough // just needs a register to hold the value from the bus
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logic CaptureEn;
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assign LSUHADDR = LSUPAdrM;
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