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Fixed RAM instantiations

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This commit is contained in:
David Harris 2023-02-19 06:31:41 -08:00
parent 2ed29792e5
commit 6d405ad69b
2 changed files with 8 additions and 3 deletions
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4
src/generic/mem/ram1p1rwbe_64x22.sv
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@ -36,7 +36,9 @@ module ram1p1rwbe_64x22(
// replace "generic64x22RAM" with "TS1N..64X22.." module from your memory vendor
// use part of a larger RAM to avoid generating more flavors of RAM
TS1N28HPCPSVTB64X44M4SW sramIP(.CLK, .CEB, .WEB, .A, .D(D[21:0]), .BWEB(BWEB[21:0]), .Q(Q[21:0]));
logic [43:0] Qfull;
TS1N28HPCPSVTB64X44M4SW sramIP(.CLK, .CEB, .WEB, .A, .D({22'b0, D[21:0]}), .BWEB({22'b0, BWEB[21:0]}), .Q(Qfull));
assign Q = Qfull[21:0];
// genericRAM #(64, 22) sramIP (.CLK, .CEB, .WEB, .A, .D, .BWEB, .Q);
endmodule

7
src/generic/mem/ram2p1r1wbe_1024x36.sv
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@ -45,8 +45,11 @@ module ram2p1r1wbe_1024x36(
//generic1024x36RAM sramIP (.CLKA, .CLKB, .CEBA, .CEBB, .WEBA, .WEBB,
// .AA, .AB, .DA, .DB, .BWEBA, .BWEBB, .QA, .QB);
// use part of a larger RAM to avoid generating more flavors of RAM
logic [67:0] QAfull, QBfull;
TSDN28HPCPA1024X68M4MW sramIP(.CLKA, .CLKB, .CEBA, .CEBB, .WEBA, .WEBB,
.AA, .AB, .DA(DA[35:0]), .DB(DB[35:0]),
.BWEBA(BWEBA[35:0]), .BWEBB(BWEBB[35:0]), .QA(QA[35:0]), .QB(QB[35:0]));
.AA, .AB, .DA({32'b0, DA[35:0]}), .DB({32'b0, DB[35:0]}),
.BWEBA({32'b0, BWEBA[35:0]}), .BWEBB({32'b0, BWEBB[35:0]}), .QA(QAfull), .QB(QBfull));
assign QA = QAfull[35:0];
assign QB = QBfull[35:0];
endmodule