forked from Github_Repos/cvw
Fixed HTRANS not changing after accepting HREADY. This exposed a bug in uncore.
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@ -140,7 +140,6 @@ module buscachefsm #(parameter integer WordCountThreshold,
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// AHB bus interface
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assign HTRANS = (CurrState == ADR_PHASE & HREADY & (|BusRW | |CacheBusRW)) |
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(CurrState == DATA_PHASE & ~HREADY) | // *** this is wrong.
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(CacheAccess & FinalWordCount & |CacheBusRW & HREADY) ? AHB_NONSEQ : // if we have a pipelined request
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(CacheAccess & |WordCount) ? (`BURST_EN ? AHB_SEQ : AHB_NONSEQ) : AHB_IDLE;
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@ -76,8 +76,7 @@ module busfsm
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assign BusCommitted = CurrState != ADR_PHASE;
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assign HTRANS = (CurrState == ADR_PHASE & HREADY & |BusRW) |
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(CurrState == DATA_PHASE & ~HREADY) ? AHB_NONSEQ : AHB_IDLE;
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assign HTRANS = (CurrState == ADR_PHASE & HREADY & |BusRW) ? AHB_NONSEQ : AHB_IDLE;
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assign HWRITE = BusRW[0];
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assign CaptureEn = CurrState == DATA_PHASE;
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@ -203,6 +203,6 @@ module uncore (
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// However on reset None must be seleted.
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flopenr #(10) hseldelayreg(HCLK, ~HRESETn, HREADY, HSELRegions[10:1], {HSELDTIMD, HSELIROMD, HSELEXTD, HSELBootRomD, HSELRamD, HSELCLINTD, HSELGPIOD, HSELUARTD, HSELPLICD, HSELSDCD});
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flopenl #(1) hseldelayreg2(HCLK, ~HRESETn, HREADY, HSELRegions[0], 1'b1, HSELNoneD);
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flopr #(1) hselbridgedelayreg(HCLK, ~HRESETn, HSELBRIDGE, HSELBRIDGED);
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flopenr #(1) hselbridgedelayreg(HCLK, ~HRESETn, HREADY, HSELBRIDGE, HSELBRIDGED);
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endmodule
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