Cleaned warning on HPTW default state

pipelined/src/mmu/hptw.sv

@@ -151,6 +151,7 @@ module hptw
 	// to decrease the latency of the HPTW.  However, if the D$ is a cycle limiter, it's better to leave the
 	// HPTW as shown below to keep the D$ setup time out of the critical path.
 	// *** Is this really true.  Talk with Ross.  Seems like it's the next state logic on critical path instead.
+	// *** address TYPE(statetype)
 	flopenl #(.TYPE(statetype)) WalkerStateReg(clk, reset, 1'b1, NextWalkerState, IDLE, WalkerState); 
 	always_comb 
 	case (WalkerState)
@@ -190,7 +191,8 @@ module hptw
 	LEAF:                       NextWalkerState = IDLE; // updates TLB
 	default: begin
 		// synthesis translate_off
-		$error("Default state in HPTW should be unreachable; was %d", WalkerState);
+		if (WalkerState !== 'x) 
+			$error("Default state in HPTW should be unreachable; was %d", WalkerState);
 		// synthesis translate_on
 		NextWalkerState = IDLE; // should never be reached
 	end

pipelined/src/privileged/privdec.sv

@@ -49,7 +49,7 @@ module privdec (
   assign ecallM =     PrivilegedM & (InstrM[31:20] == 12'b000000000000);
   assign ebreakM =    PrivilegedM & (InstrM[31:20] == 12'b000000000001);
   assign wfiM =       PrivilegedM & (InstrM[31:20] == 12'b000100000101);
-  assign sfencevmaM = PrivilegedM & (InstrM[31:25] ==  7'b0001001);
+  assign sfencevmaM = PrivilegedM & (InstrM[31:25] ==  7'b0001001); // *** & (PrivilegedModeW == `M_MODE | ~STATUS_TVM); // *** does this work in U mode?
   assign IllegalPrivilegedInstrM = PrivilegedM & ~(sretM|mretM|ecallM|ebreakM|wfiM|sfencevmaM);
   assign IllegalInstrFaultM = (IllegalIEUInstrFaultM & IllegalFPUInstrM) | IllegalPrivilegedInstrM | IllegalCSRAccessM | TrappedSRETM; // *** generalize this for other instructions