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added mstatus uxl, sxl bit tests (not tested in regression yet)

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Kip Macsai-Goren 2022-09-18 00:11:29 +00:00
parent dda3b2d383
commit 3f4c825a1a
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4
tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-status-xlen-01.reference_output Normal file
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00000000 # Test *** Number : Read out SXL, UXL of mstatus as 2 and 2 for 64 bit systems
0000000a
00000000 # read of read-only uxl, sxl bits after attmepted write
0000000a

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tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-status-xlen-01.S Normal file
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///////////////////////////////////////////
//
// WALLY-status-xlen
//
// Author: Kip Macsai-Goren <kmacsaigoren@g.hmc.edu>
//
// Created 2022-09-17
//
// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
//
// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy,
// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software
// is furnished to do so, subject to the following conditions:
//
// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
//
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
///////////////////////////////////////////
#include "WALLY-TEST-LIB-64.h"
RVTEST_ISA("RV64I")
RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*);def TEST_CASE_1=True;",endianness)
INIT_TESTS
TRAP_HANDLER m
// Test ***Number: check that the UXL and SXL bits of mstatus are read only and the correct value (2 for 64 bit systems)
csrr x28, mstatus
li x29, 0xF00000000 // mask bits for uxl and sxl
and x28, x28, x29
sd x28, 0(t1) // should store 0xA00000000 to memory
addi t1, t1, 8
addi a6, a6, 8
csrs mstatus, x29 // attempt to write to uxl and sxl, should not work
csrr x28, mstatus
and x28, x28, x29
sd x28, 0(t1) // should store 0xA00000000 to memory
addi t1, t1, 8
addi a6, a6, 8
END_TESTS
TEST_STACK_AND_DATA