Xavi/cvw
1
0
Fork 0
forked from Github_Repos/cvw
Code Issues Pull Requests Packages Projects Releases Wiki Activity

removed old unused tests from wally arch tests

Browse Source
This commit is contained in:
Kip Macsai-Goren 2022-04-27 18:30:21 +00:00
parent 2f17edb5f4
commit c47ec36bc7
31 changed files with 1 additions and 35777 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

15
pipelined/testbench/tests.vh
View File

@ -1454,26 +1454,13 @@ string imperas32f[] = '{
string wally64priv[] = '{
`WALLYTEST,
"rv64i_m/privilege/WALLY-CSR-permission-s-01", "0060a0",
//"rv64i_m/privilege/WALLY-CSR-PERMISSIONS-M", "005090",
//"rv64i_m/privilege/WALLY-CSR-PERMISSIONS-S", "003090",
"rv64i_m/privilege/WALLY-CSR-permission-u-01", "0060a0",
// "rv64i_m/privilege/WALLY-MARCHID", "004090",
/* "rv64i_m/privilege/WALLY-MCAUSE", "003090",
"rv64i_m/privilege/WALLY-MEDELEG", "004090",
"rv64i_m/privilege/WALLY-MHARTID", "004090",
"rv64i_m/privilege/WALLY-MIMPID", "004090",*/
"rv64i_m/privilege/WALLY-minfo-01", "0050a0",
"rv64i_m/privilege/WALLY-misa-01", "0050a0",
"rv64i_m/privilege/WALLY-MMU-SV39", "0050a0",
"rv64i_m/privilege/WALLY-MMU-SV48", "0050a0",
/* "rv64i_m/privilege/WALLY-MSTATUS", "002090",
"rv64i_m/privilege/WALLY-MTVEC", "002090",
"rv64i_m/privilege/WALLY-MVENDORID", "004090", */
"rv64i_m/privilege/WALLY-PMA", "0050a0",
"rv64i_m/privilege/WALLY-PMP", "0050a0",
// "rv64i_m/privilege/WALLY-SCAUSE", "002090",
// "rv64i_m/privilege/WALLY-scratch-01", "0040a0",
// "rv64i_m/privilege/WALLY-sscratch-s-01", "0040a0",
"rv64i_m/privilege/WALLY-trap-01", "0050a0",
"rv64i_m/privilege/WALLY-trap-s-01", "0050a0",
"rv64i_m/privilege/WALLY-trap-u-01", "0050a0",
@ -1486,8 +1473,6 @@ string imperas32f[] = '{
// "rv64i_m/privilege/WALLY-status-tw-01", "0050a0",
"rv64i_m/privilege/WALLY-WFI-01", "0050a0",
"rv64i_m/privilege/WALLY-status-fp-disabled-01", "50a0"
// "rv64i_m/privilege/WALLY-STVEC", "002090",
// "rv64i_m/privilege/WALLY-UCAUSE", "002090",
};

27
tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/Makefrag
View File

@ -38,28 +38,11 @@ rv64i_sc_tests = \
WALLY-AMO \
WALLY-LRSC \
WALLY-trap-sret-01 \
# WALLY-scratch-01 \
# WALLY-sscratch-s-01 \
# WALLY-scratch-01 \
# Don't simulate these because they rely on SoC features that Wally does not offer.
# Don't simulate these because they rely on SoC features that Spike does not offer.
target_tests_nosim = \
WALLY-PMA \
WALLY-PERIPH \
WALLY-MSTATUS \
WALLY-MCAUSE \
WALLY-SCAUSE \
WALLY-UCAUSE \
WALLY-MTVEC \
WALLY-STVEC \
WALLY-MEDELEG \
WALLY-MARCHID \
WALLY-MHARTID \
WALLY-MIMPID \
WALLY-MVENDORID \
WALLY-CSR-PERMISSIONS-M \
WALLY-CSR-PERMISSIONS-S \
WALLY-mtvec-01 \
WALLY-stvec-01 \
WALLY-MIE-01 \
@ -72,14 +55,6 @@ target_tests_nosim = \
WALLY-WFI-01 \
WALLY-status-fp-enabled-01 \
WALLY-status-fp-disabled-01 \
# Have all 0's in references!
#WALLY-MEPC \
#WALLY-SEPC \
#WALLY-MTVAL \
#WALLY-STVAL \
# Otherwise Broken for Unknown Reasons
#WALLY-MIE \
#WALLY-IP \
rv64i_tests = $(addsuffix .elf, $(rv64i_sc_tests))

1008
tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-CSR-PERMISSIONS-M.reference_output
View File

File diff suppressed because it is too large Load Diff

336
tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-CSR-PERMISSIONS-S.reference_output
View File

@ -1,336 +0,0 @@
00000002
00000000
00000002
00000000
00000002
00000000
00000002
00000000
00000002
00000000
00000002
00000000
00000002
00000000
00000002
00000000
00000002
00000000
00000002
00000000
00000002
00000000
00000002
00000000
00000002
00000000
00000002
00000000
00000002
00000000
00000002
00000000
00000002
00000000
00000002
00000000
00000002
00000000
00000002
00000000
00000002
00000000
00000002
00000000
00000002
00000000
00000002
00000000
00000002
00000000
00000002
00000000
00000002
00000000
00000002
00000000
00000002
00000000
00000002
00000000
00000002
00000000
00000002
00000000
00000002
00000000
00000002
00000000
00000002
00000000
00000002
00000000
00000002
00000000
00000002
00000000
00000002
00000000
00000002
00000000
00000002
00000000
00000002
00000000
00000002
00000000
00000002
00000000
00000002
00000000
00000002
00000000
00000002
00000000
00000002
00000000
00000002
00000000
00000002
00000000
00000002
00000000
00000002
00000000
00000002
00000000
00000002
00000000
00000002
00000000
00000002
00000000
00000002
00000000
00000002
00000000
00000002
00000000
00000002
00000000
00000002
00000000
00000002
00000000
00000002
00000000
00000002
00000000
00000002
00000000
00000002
00000000
00000002
00000000
00000002
00000000
00000002
00000000
00000002
00000000
00000002
00000000
00000002
00000000
00000002
00000000
00000002
00000000
00000002
00000000
00000002
00000000
00000002
00000000
00000002
00000000
00000002
00000000
00000002
00000000
00000002
00000000
00000002
00000000
00000002
00000000
00000002
00000000
00000002
00000000
00000002
00000000
00000002
00000000
00000002
00000000
00000002
00000000
00000002
00000000
00000002
00000000
00000002
00000000
00000002
00000000
00000002
00000000
00000002
00000000
00000002
00000000
00000002
00000000
00000002
00000000
00000002
00000000
00000002
00000000
00000002
00000000
00000002
00000000
00000002
00000000
00000002
00000000
00000002
00000000
00000002
00000000
00000002
00000000
00000002
00000000
00000002
00000000
00000002
00000000
00000002
00000000
00000002
00000000
00000002
00000000
00000002
00000000
00000002
00000000
00000002
00000000
00000002
00000000
00000002
00000000
00000002
00000000
00000002
00000000
00000002
00000000
00000002
00000000
00000002
00000000
00000002
00000000
00000002
00000000
00000002
00000000
00000002
00000000
00000002
00000000
00000002
00000000
00000002
00000000
00000002
00000000
00000002
00000000
00000002
00000000
00000002
00000000
00000002
00000000
00000002
00000000
00000002
00000000
00000002
00000000
00000002
00000000
00000002
00000000
00000002
00000000
00000002
00000000
00000002
00000000
00000002
00000000
00000002
00000000
00000002
00000000
00000002
00000000
00000002
00000000
00000002
00000000
00000002
00000000
00000002
00000000
00000002
00000000
00000002
00000000
00000002
00000000
00000002
00000000
00000002
00000000
00000002
00000000
00000002
00000000
00000002
00000000
00000002
00000000
00000002
00000000
00000002
00000000
00000002
00000000
00000002
00000000
00000002
00000000
00000002
00000000
00000002
00000000
00000002
00000000

392
tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-MARCHID.reference_output
View File

@ -1,392 +0,0 @@
00000002
00000000
00000000
00000000
00000002
00000000
00000000
00000000
00000002
00000000
00000000
00000000
00000002
00000000
00000000
00000000
00000002
00000000
00000000
00000000
00000002
00000000
00000000
00000000
00000002
00000000
00000000
00000000
00000002
00000000
00000000
00000000
00000002
00000000
00000000
00000000
00000002
00000000
00000000
00000000
00000002
00000000
00000000
00000000
00000002
00000000
00000000
00000000
00000002
00000000
00000000
00000000
00000002
00000000
00000000
00000000
00000002
00000000
00000000
00000000
00000002
00000000
00000000
00000000
00000002
00000000
00000000
00000000
00000002
00000000
00000000
00000000
00000002
00000000
00000000
00000000
00000002
00000000
00000000
00000000
00000002
00000000
00000000
00000000
00000002
00000000
00000000
00000000
00000002
00000000
00000000
00000000
00000002
00000000
00000000
00000000
00000002
00000000
00000000
00000000
00000002
00000000
00000000
00000000
00000002
00000000
00000000
00000000
00000002
00000000
00000000
00000000
00000002
00000000
00000000
00000000
00000002
00000000
00000000
00000000
00000002
00000000
00000000
00000000
00000002
00000000
00000000
00000000
00000002
00000000
00000000
00000000
00000002
00000000
00000000
00000000
00000002
00000000
00000000
00000000
00000002
00000000
00000000
00000000
00000002
00000000
00000000
00000000
00000002
00000000
00000000
00000000
00000002
00000000
00000000
00000000
00000002
00000000
00000000
00000000
00000002
00000000
00000000
00000000
00000002
00000000
00000000
00000000
00000002
00000000
00000000
00000000
00000002
00000000
00000000
00000000
00000002
00000000
00000000
00000000
00000002
00000000
00000000
00000000
00000002
00000000
00000000
00000000
00000002
00000000
00000000
00000000
00000002
00000000
00000000
00000000
00000002
00000000
00000000
00000000
00000002
00000000
00000000
00000000
00000002
00000000
00000000
00000000
00000002
00000000
00000000
00000000
00000002
00000000
00000000
00000000
00000002
00000000
00000000
00000000
00000002
00000000
00000000
00000000
00000002
00000000
00000000
00000000
00000002
00000000
00000000
00000000
00000002
00000000
00000000
00000000
00000002
00000000
00000000
00000000
00000002
00000000
00000000
00000000
00000002
00000000
00000000
00000000
00000002
00000000
00000000
00000000
00000002
00000000
00000000
00000000
00000002
00000000
00000000
00000000
00000002
00000000
00000000
00000000
00000002
00000000
00000000
00000000
00000002
00000000
00000000
00000000
00000002
00000000
00000000
00000000
00000002
00000000
00000000
00000000
00000002
00000000
00000000
00000000
00000002
00000000
00000000
00000000
00000002
00000000
00000000
00000000
00000002
00000000
00000000
00000000
00000002
00000000
00000000
00000000
00000002
00000000
00000000
00000000
00000002
00000000
00000000
00000000
00000002
00000000
00000000
00000000
00000002
00000000
00000000
00000000
00000002
00000000
00000000
00000000
00000002
00000000
00000000
00000000
00000002
00000000
00000000
00000000
00000002
00000000
00000000
00000000
00000002
00000000
00000000
00000000
00000002
00000000
00000000
00000000
00000002
00000000
00000000
00000000
00000002
00000000
00000000
00000000
00000002
00000000
00000000
00000000
00000002
00000000
00000000
00000000
00000002
00000000
00000000
00000000
00000002
00000000
00000000
00000000
00000002
00000000
00000000
00000000
00000002
00000000
00000000
00000000
00000002
00000000
00000000
00000000
00000002
00000000
00000000
00000000
00000002
00000000
00000000
00000000
00000002
00000000
00000000
00000000
00000002
00000000
00000000
00000000

208
tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-MCAUSE.reference_output
View File

@ -1,208 +0,0 @@
00000007
80000000
00000002
00000000
00000004
00000000
00000006
00000000
0000000b
00000000
00000007
80000000
00000002
00000000
00000004
00000000
00000006
00000000
0000000b
00000000
00000007
80000000
00000002
00000000
00000004
00000000
00000006
00000000
0000000b
00000000
00000007
80000000
00000002
00000000
00000004
00000000
00000006
00000000
0000000b
00000000
00000007
80000000
00000002
00000000
00000004
00000000
00000006
00000000
0000000b
00000000
00000007
80000000
00000002
00000000
00000004
00000000
00000006
00000000
0000000b
00000000
00000007
80000000
00000002
00000000
00000004
00000000
00000006
00000000
0000000b
00000000
00000007
80000000
00000002
00000000
00000004
00000000
00000006
00000000
0000000b
00000000
00000002
00000000
00000004
00000000
00000006
00000000
00000009
00000000
00000002
00000000
00000004
00000000
00000006
00000000
00000009
00000000
00000002
00000000
00000004
00000000
00000006
00000000
00000009
00000000
00000002
00000000
00000004
00000000
00000006
00000000
00000009
00000000
00000002
00000000
00000004
00000000
00000006
00000000
00000009
00000000
00000002
00000000
00000004
00000000
00000006
00000000
00000009
00000000
00000002
00000000
00000004
00000000
00000006
00000000
00000009
00000000
00000002
00000000
00000004
00000000
00000006
00000000
00000009
00000000
00000002
00000000
00000004
00000000
00000006
00000000
00000008
00000000
00000002
00000000
00000004
00000000
00000006
00000000
00000008
00000000
00000002
00000000
00000004
00000000
00000006
00000000
00000008
00000000
00000002
00000000
00000004
00000000
00000006
00000000
00000008
00000000
00000002
00000000
00000004
00000000
00000006
00000000
00000008
00000000
00000002
00000000
00000004
00000000
00000006
00000000
00000008
00000000
00000002
00000000
00000004
00000000
00000006
00000000
00000008
00000000
00000002
00000000
00000004
00000000
00000006
00000000
00000008
00000000

120
tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-MEDELEG.reference_output
View File

@ -1,120 +0,0 @@
00000003
00000000
00000003
00000000
00000001
00000000
00000003
00000000
00000001
00000000
00000003
00000000
00000003
00000000
00000003
00000000
00000001
00000000
00000003
00000000
00000001
00000000
00000003
00000000
00000003
00000000
00000003
00000000
00000001
00000000
00000003
00000000
00000001
00000000
00000003
00000000
00000003
00000000
00000003
00000000
00000001
00000000
00000003
00000000
00000001
00000000
00000003
00000000
00000003
00000000
00000003
00000000
00000001
00000000
00000003
00000000
00000001
00000000
00000003
00000000
00000003
00000000
00000003
00000000
00000001
00000000
00000003
00000000
00000001
00000000
00000003
00000000
00000003
00000000
00000003
00000000
00000001
00000000
00000003
00000000
00000001
00000000
00000003
00000000
00000003
00000000
00000003
00000000
00000001
00000000
00000003
00000000
00000001
00000000
00000003
00000000
00000003
00000000
00000003
00000000
00000001
00000000
00000003
00000000
00000001
00000000
00000003
00000000
00000003
00000000
00000003
00000000
00000001
00000000
00000003
00000000
00000001
00000000
00000003
00000000

392
tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-MHARTID.reference_output
View File

@ -1,392 +0,0 @@
00000002
00000000
00000000
00000000
00000002
00000000
00000000
00000000
00000002
00000000
00000000
00000000
00000002
00000000
00000000
00000000
00000002
00000000
00000000
00000000
00000002
00000000
00000000
00000000
00000002
00000000
00000000
00000000
00000002
00000000
00000000
00000000
00000002
00000000
00000000
00000000
00000002
00000000
00000000
00000000
00000002
00000000
00000000
00000000
00000002
00000000
00000000
00000000
00000002
00000000
00000000
00000000
00000002
00000000
00000000
00000000
00000002
00000000
00000000
00000000
00000002
00000000
00000000
00000000
00000002
00000000
00000000
00000000
00000002
00000000
00000000
00000000
00000002
00000000
00000000
00000000
00000002
00000000
00000000
00000000
00000002
00000000
00000000
00000000
00000002
00000000
00000000
00000000
00000002
00000000
00000000
00000000
00000002
00000000
00000000
00000000
00000002
00000000
00000000
00000000
00000002
00000000
00000000
00000000
00000002
00000000
00000000
00000000
00000002
00000000
00000000
00000000
00000002
00000000
00000000
00000000
00000002
00000000
00000000
00000000
00000002
00000000
00000000
00000000
00000002
00000000
00000000
00000000
00000002
00000000
00000000
00000000
00000002
00000000
00000000
00000000
00000002
00000000
00000000
00000000
00000002
00000000
00000000
00000000
00000002
00000000
00000000
00000000
00000002
00000000
00000000
00000000
00000002
00000000
00000000
00000000
00000002
00000000
00000000
00000000
00000002
00000000
00000000
00000000
00000002
00000000
00000000
00000000
00000002
00000000
00000000
00000000
00000002
00000000
00000000
00000000
00000002
00000000
00000000
00000000
00000002
00000000
00000000
00000000
00000002
00000000
00000000
00000000
00000002
00000000
00000000
00000000
00000002
00000000
00000000
00000000
00000002
00000000
00000000
00000000
00000002
00000000
00000000
00000000
00000002
00000000
00000000
00000000
00000002
00000000
00000000
00000000
00000002
00000000
00000000
00000000
00000002
00000000
00000000
00000000
00000002
00000000
00000000
00000000
00000002
00000000
00000000
00000000
00000002
00000000
00000000
00000000
00000002
00000000
00000000
00000000
00000002
00000000
00000000
00000000
00000002
00000000
00000000
00000000
00000002
00000000
00000000
00000000
00000002
00000000
00000000
00000000
00000002
00000000
00000000
00000000
00000002
00000000
00000000
00000000
00000002
00000000
00000000
00000000
00000002
00000000
00000000
00000000
00000002
00000000
00000000
00000000
00000002
00000000
00000000
00000000
00000002
00000000
00000000
00000000
00000002
00000000
00000000
00000000
00000002
00000000
00000000
00000000
00000002
00000000
00000000
00000000
00000002
00000000
00000000
00000000
00000002
00000000
00000000
00000000
00000002
00000000
00000000
00000000
00000002
00000000
00000000
00000000
00000002
00000000
00000000
00000000
00000002
00000000
00000000
00000000
00000002
00000000
00000000
00000000
00000002
00000000
00000000
00000000
00000002
00000000
00000000
00000000
00000002
00000000
00000000
00000000
00000002
00000000
00000000
00000000
00000002
00000000
00000000
00000000
00000002
00000000
00000000
00000000
00000002
00000000
00000000
00000000
00000002
00000000
00000000
00000000
00000002
00000000
00000000
00000000
00000002
00000000
00000000
00000000
00000002
00000000
00000000
00000000
00000002
00000000
00000000
00000000
00000002
00000000
00000000
00000000
00000002
00000000
00000000
00000000
00000002
00000000
00000000
00000000
00000002
00000000
00000000
00000000
00000002
00000000
00000000
00000000
00000002
00000000
00000000
00000000

392
tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-MIMPID.reference_output
View File

@ -1,392 +0,0 @@
00000002
00000000
00000000
00000000
00000002
00000000
00000000
00000000
00000002
00000000
00000000
00000000
00000002
00000000
00000000
00000000
00000002
00000000
00000000
00000000
00000002
00000000
00000000
00000000
00000002
00000000
00000000
00000000
00000002
00000000
00000000
00000000
00000002
00000000
00000000
00000000
00000002
00000000
00000000
00000000
00000002
00000000
00000000
00000000
00000002
00000000
00000000
00000000
00000002
00000000
00000000
00000000
00000002
00000000
00000000
00000000
00000002
00000000
00000000
00000000
00000002
00000000
00000000
00000000
00000002
00000000
00000000
00000000
00000002
00000000
00000000
00000000
00000002
00000000
00000000
00000000
00000002
00000000
00000000
00000000
00000002
00000000
00000000
00000000
00000002
00000000
00000000
00000000
00000002
00000000
00000000
00000000
00000002
00000000
00000000
00000000
00000002
00000000
00000000
00000000
00000002
00000000
00000000
00000000
00000002
00000000
00000000
00000000
00000002
00000000
00000000
00000000
00000002
00000000
00000000
00000000
00000002
00000000
00000000
00000000
00000002
00000000
00000000
00000000
00000002
00000000
00000000
00000000
00000002
00000000
00000000
00000000
00000002
00000000
00000000
00000000
00000002
00000000
00000000
00000000
00000002
00000000
00000000
00000000
00000002
00000000
00000000
00000000
00000002
00000000
00000000
00000000
00000002
00000000
00000000
00000000
00000002
00000000
00000000
00000000
00000002
00000000
00000000
00000000
00000002
00000000
00000000
00000000
00000002
00000000
00000000
00000000
00000002
00000000
00000000
00000000
00000002
00000000
00000000
00000000
00000002
00000000
00000000
00000000
00000002
00000000
00000000
00000000
00000002
00000000
00000000
00000000
00000002
00000000
00000000
00000000
00000002
00000000
00000000
00000000
00000002
00000000
00000000
00000000
00000002
00000000
00000000
00000000
00000002
00000000
00000000
00000000
00000002
00000000
00000000
00000000
00000002
00000000
00000000
00000000
00000002
00000000
00000000
00000000
00000002
00000000
00000000
00000000
00000002
00000000
00000000
00000000
00000002
00000000
00000000
00000000
00000002
00000000
00000000
00000000
00000002
00000000
00000000
00000000
00000002
00000000
00000000
00000000
00000002
00000000
00000000
00000000
00000002
00000000
00000000
00000000
00000002
00000000
00000000
00000000
00000002
00000000
00000000
00000000
00000002
00000000
00000000
00000000
00000002
00000000
00000000
00000000
00000002
00000000
00000000
00000000
00000002
00000000
00000000
00000000
00000002
00000000
00000000
00000000
00000002
00000000
00000000
00000000
00000002
00000000
00000000
00000000
00000002
00000000
00000000
00000000
00000002
00000000
00000000
00000000
00000002
00000000
00000000
00000000
00000002
00000000
00000000
00000000
00000002
00000000
00000000
00000000
00000002
00000000
00000000
00000000
00000002
00000000
00000000
00000000
00000002
00000000
00000000
00000000
00000002
00000000
00000000
00000000
00000002
00000000
00000000
00000000
00000002
00000000
00000000
00000000
00000002
00000000
00000000
00000000
00000002
00000000
00000000
00000000
00000002
00000000
00000000
00000000
00000002
00000000
00000000
00000000
00000002
00000000
00000000
00000000
00000002
00000000
00000000
00000000
00000002
00000000
00000000
00000000
00000002
00000000
00000000
00000000
00000002
00000000
00000000
00000000
00000002
00000000
00000000
00000000
00000002
00000000
00000000
00000000
00000002
00000000
00000000
00000000
00000002
00000000
00000000
00000000
00000002
00000000
00000000
00000000

16
tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-MSTATUS.reference_output
View File

@ -1,16 +0,0 @@
00000000
00000000
00000000
000000D5
0000005D
00006410
00000146
00001800
00000000
00000000
00000000
00000000
00000100
00000000
00000000
FFFFFFFF

96
tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-MTVEC.reference_output
View File

@ -1,96 +0,0 @@
00000000
00000000
00000001
00000000
00000000
00000000
00000001
00000000
00000004
00000000
00000005
00000000
00000004
00000000
00000005
00000000
00000008
00000000
00000009
00000000
00000008
00000000
00000009
00000000
0000000c
00000000
0000000d
00000000
0000000c
00000000
0000000d
00000000
00000000
00000000
00000007
00000000
00000000
00000000
00000007
00000000
00000000
00000000
00000007
00000000
00000000
00000000
00000007
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000

392
tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-MVENDORID.reference_output
View File

@ -1,392 +0,0 @@
00000002
00000000
00000000
00000000
00000002
00000000
00000000
00000000
00000002
00000000
00000000
00000000
00000002
00000000
00000000
00000000
00000002
00000000
00000000
00000000
00000002
00000000
00000000
00000000
00000002
00000000
00000000
00000000
00000002
00000000
00000000
00000000
00000002
00000000
00000000
00000000
00000002
00000000
00000000
00000000
00000002
00000000
00000000
00000000
00000002
00000000
00000000
00000000
00000002
00000000
00000000
00000000
00000002
00000000
00000000
00000000
00000002
00000000
00000000
00000000
00000002
00000000
00000000
00000000
00000002
00000000
00000000
00000000
00000002
00000000
00000000
00000000
00000002
00000000
00000000
00000000
00000002
00000000
00000000
00000000
00000002
00000000
00000000
00000000
00000002
00000000
00000000
00000000
00000002
00000000
00000000
00000000
00000002
00000000
00000000
00000000
00000002
00000000
00000000
00000000
00000002
00000000
00000000
00000000
00000002
00000000
00000000
00000000
00000002
00000000
00000000
00000000
00000002
00000000
00000000
00000000
00000002
00000000
00000000
00000000
00000002
00000000
00000000
00000000
00000002
00000000
00000000
00000000
00000002
00000000
00000000
00000000
00000002
00000000
00000000
00000000
00000002
00000000
00000000
00000000
00000002
00000000
00000000
00000000
00000002
00000000
00000000
00000000
00000002
00000000
00000000
00000000
00000002
00000000
00000000
00000000
00000002
00000000
00000000
00000000
00000002
00000000
00000000
00000000
00000002
00000000
00000000
00000000
00000002
00000000
00000000
00000000
00000002
00000000
00000000
00000000
00000002
00000000
00000000
00000000
00000002
00000000
00000000
00000000
00000002
00000000
00000000
00000000
00000002
00000000
00000000
00000000
00000002
00000000
00000000
00000000
00000002
00000000
00000000
00000000
00000002
00000000
00000000
00000000
00000002
00000000
00000000
00000000
00000002
00000000
00000000
00000000
00000002
00000000
00000000
00000000
00000002
00000000
00000000
00000000
00000002
00000000
00000000
00000000
00000002
00000000
00000000
00000000
00000002
00000000
00000000
00000000
00000002
00000000
00000000
00000000
00000002
00000000
00000000
00000000
00000002
00000000
00000000
00000000
00000002
00000000
00000000
00000000
00000002
00000000
00000000
00000000
00000002
00000000
00000000
00000000
00000002
00000000
00000000
00000000
00000002
00000000
00000000
00000000
00000002
00000000
00000000
00000000
00000002
00000000
00000000
00000000
00000002
00000000
00000000
00000000
00000002
00000000
00000000
00000000
00000002
00000000
00000000
00000000
00000002
00000000
00000000
00000000
00000002
00000000
00000000
00000000
00000002
00000000
00000000
00000000
00000002
00000000
00000000
00000000
00000002
00000000
00000000
00000000
00000002
00000000
00000000
00000000
00000002
00000000
00000000
00000000
00000002
00000000
00000000
00000000
00000002
00000000
00000000
00000000
00000002
00000000
00000000
00000000
00000002
00000000
00000000
00000000
00000002
00000000
00000000
00000000
00000002
00000000
00000000
00000000
00000002
00000000
00000000
00000000
00000002
00000000
00000000
00000000
00000002
00000000
00000000
00000000
00000002
00000000
00000000
00000000
00000002
00000000
00000000
00000000
00000002
00000000
00000000
00000000
00000002
00000000
00000000
00000000
00000002
00000000
00000000
00000000
00000002
00000000
00000000
00000000
00000002
00000000
00000000
00000000
00000002
00000000
00000000
00000000
00000002
00000000
00000000
00000000
00000002
00000000
00000000
00000000
00000002
00000000
00000000
00000000

128
tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-SCAUSE.reference_output
View File

@ -1,128 +0,0 @@
00000002
00000000
00000004
00000000
00000006
00000000
00000009
00000000
00000002
00000000
00000004
00000000
00000006
00000000
00000009
00000000
00000002
00000000
00000004
00000000
00000006
00000000
00000009
00000000
00000002
00000000
00000004
00000000
00000006
00000000
00000009
00000000
00000002
00000000
00000004
00000000
00000006
00000000
00000009
00000000
00000002
00000000
00000004
00000000
00000006
00000000
00000009
00000000
00000002
00000000
00000004
00000000
00000006
00000000
00000009
00000000
00000002
00000000
00000004
00000000
00000006
00000000
00000009
00000000
00000002
00000000
00000004
00000000
00000006
00000000
00000008
00000000
00000002
00000000
00000004
00000000
00000006
00000000
00000008
00000000
00000002
00000000
00000004
00000000
00000006
00000000
00000008
00000000
00000002
00000000
00000004
00000000
00000006
00000000
00000008
00000000
00000002
00000000
00000004
00000000
00000006
00000000
00000008
00000000
00000002
00000000
00000004
00000000
00000006
00000000
00000008
00000000
00000002
00000000
00000004
00000000
00000006
00000000
00000008
00000000
00000002
00000000
00000004
00000000
00000006
00000000
00000008
00000000

64
tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-STVEC.reference_output
View File

@ -1,64 +0,0 @@
00000000
00000000
00000001
00000000
00000000
00000000
00000001
00000000
00000004
00000000
00000005
00000000
00000004
00000000
00000005
00000000
00000008
00000000
00000009
00000000
00000008
00000000
00000009
00000000
0000000c
00000000
0000000d
00000000
0000000c
00000000
0000000d
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000

80
tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-UCAUSE.reference_output
View File

@ -1,80 +0,0 @@
00000002
00000000
00000003
00000000
00000004
00000000
00000006
00000000
00000008
00000000
00000002
00000000
00000003
00000000
00000004
00000000
00000006
00000000
00000008
00000000
00000002
00000000
00000003
00000000
00000004
00000000
00000006
00000000
00000008
00000000
00000002
00000000
00000003
00000000
00000004
00000000
00000006
00000000
00000008
00000000
00000002
00000000
00000003
00000000
00000004
00000000
00000006
00000000
00000008
00000000
00000002
00000000
00000003
00000000
00000004
00000000
00000006
00000000
00000008
00000000
00000002
00000000
00000003
00000000
00000004
00000000
00000006
00000000
00000008
00000000
00000002
00000000
00000003
00000000
00000004
00000000
00000006
00000000
00000008
00000000

1024
tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-scratch-01.reference_output
View File

File diff suppressed because it is too large Load Diff

1024
tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-sscratch-s-01.reference_output
View File

File diff suppressed because it is too large Load Diff

5265
tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-CSR-PERMISSIONS-M.S
View File

File diff suppressed because it is too large Load Diff

2627
tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-CSR-PERMISSIONS-S.S
View File

File diff suppressed because it is too large Load Diff

3778
tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-MARCHID.S
View File

File diff suppressed because it is too large Load Diff

2324
tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-MCAUSE.S
View File

File diff suppressed because it is too large Load Diff

3675
tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-MEDELEG.S
View File

File diff suppressed because it is too large Load Diff

3778
tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-MHARTID.S
View File

File diff suppressed because it is too large Load Diff

433
tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-MSTATUS.S
View File

@ -1,433 +0,0 @@
///////////////////////////////////////////
//
// /imperas-riscv-tests/riscv-test-suite/rv64d/src/WALLY-MSTATUS-rv64d.S
//
// Generated by kmacsaigoren@hmc.edu
// Created on 2021-05-24 13:03:13.519323
//
// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
// Adapted from Imperas RISCV-TEST_SUITE
//
// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy,
// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software
// is furnished to do so, subject to the following conditions:
//
// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
//
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
///////////////////////////////////////////
######################################################################
# Notes:
#
# The following bitfeilds of mstatus are left untested in this file:
# (as of 25 May 2021)
#
# SXL, UXL (unsupported, hardware depends on XLEN)
# MBE, SBE, UBE (unsupported, endianness is constant)
# TSR, TW, TVM, MXR
# XS (extra extensions not supported)
# MPRV and SUM will be tested as part of the mmu
#######################################################################
#include "model_test.h"
#include "arch_test.h"
RVTEST_ISA("RV64I")
.section .text.init
.globl rvtest_entry_point
rvtest_entry_point:
RVMODEL_BOOT
# ---------------------------------------------------------------------------------------------
# address for test results
la x6, wally_signature
###########################
# Test Code
###########################
# I sectioned each test into smaller 'functions' with labels to help organize
# and make the code a little more readable
xs_test:
# test hardwiring of xs to zero
csrr x8, mstatus
li x5, 3 # load mask bits into x5
slli x5, x5, 15
jal checkBits
# try to write 11 to xs bits to test hardwiring to zero
li x5, 3
slli x5, x5, 15
csrs mstatus, x5
jal checkBits
li x7, 1
slli x7, x7, 5 # mask out F_SUPPORTED bit
csrr x5, misa
and x5, x5, x7
bnez x5, float_supported
j float_unsupported
float_supported:
# *** KMG 6 July 2021: This test DOES NOT satisfactorily test the fs bit, for now it just chekcs that the initial value is zero
# and that it can be written but not much else.
# floating point supported, test, fs, sd bits
li x5, 3
slli x5, x5, 13 # load fs mask bits into x5
jal checkBits # should be zero since, even though float is supported, the unit hasn't been turned on *** is this true?
jal checkSD
# force fs to be 11, check SD == 1
li x5, 3
slli x5, x5, 13 # load fs mask bits into x5
csrs mstatus, x5
jal checkSD
j test_gpio
float_unsupported:
# write the same things to memory as if f was supported
sw x0, 0(x6) # initial FS value is zero
li x5, 0xD5
sw x5, 4(x6) # sd = 0
li x5, 0x5D
sw x5, 8(x6) # sd = 1
addi x6, x6, 12
test_gpio:
# Test MIE bits with GPIO interrupt
# set trap handler for GPIO interrupt
la x5, GPIOTrapHandler
csrw mtvec, x5
# load interrupt complete flag into x10
li x10, 0
# x7 holds 0x6410 if we go through an interrupt and 0x0146 if not.
li x7, 0x0146
jal configPLIC
jal configGPIO
# set mie
li x5, 0x800
csrs mie, x5
# delegate interrupts to machine mode
li x5, 0xD00
csrc mideleg, x5
# set MIE bit
li x5, 8
csrs mstatus, x5
# Cause GPIO interrupt
li x5, 0x10060000
li x28, 0x00080000
sw x28, 0x0C(x5)
# wait for GPIO interrupt to finish.
2: beq x0,x10,2b
test_gpio_disabled:
# Test MIE bit with GPIO interrupt
# set trap handler for GPIO interrupt
la x5, GPIOTrapHandler
csrw mtvec, x5
# load interrupt complete flag into x10
li x10, 0
# x7 holds 0x6410 if we go through an interrupt and 0x0146 if not.
li x7, 0x0146
# clear MIE bit
li x5, 8
csrc mstatus, x5
# Cause GPIO interrupt (shouldn't happen)
li x5, 0x10060000
li x28, 0x00080000
sw x28, 0x0C(x5)
# Dont need to wait for handler to work since interrupt doesnt happen.
sw x7, 0(x6)
addi x6, x6, 4
priv_stack_testM:
# test the privilege stack using ecall.
# set trap handler(s)
la x5, stackTrapHandlerM
csrw mtvec, x5
# begin in machine mode.
csrr x28, mstatus
# cause m mode exception.
ecall
priv_stack_testS:
# test the privilege stack using ecall, handling trap in S mode
li x5, 1
slli x5, x5, 9 # mask out ecall_S_mode for medeleg
csrs medeleg, x5 # delegate traps to S Mode
# set trap handler(s)
la x5, stackTrapHandlerS
csrw stvec, x5
jal go_supervisor_mode
csrr x28, sstatus
# cause s mode exception.
ecall
j done
#########################################
# Functions/helpers
#########################################
checkBits:
# when we load the mask bits into x5, this function stores the masked mstatus to the output
csrr x8, mstatus
and x5, x5, x8
sw x5, 0(x6)
addi x6, x6, 4
li x5, 0
ret
checkBitsS:
# same as checkbits, but checks the sstatus csr
csrr x8, sstatus
and x5, x5, x8
sw x5, 0(x6)
addi x6, x6, 4
li x5, 0
ret
checkSD:
# checks SD specially because its the first bit, so we don't have to mask.
csrr x8, mstatus
li x5, 0x5D # SD == 1
bltz x8, sdDirty
li x5, 0xD5 # SD == 0
sdDirty:
sw x5, 0(x6)
addi x6, x6, 4
ret
go_supervisor_mode:
# taken from wally final report spr 2021
li x28, 3
slli x28, x28, 11
csrc mstatus, x28 # clear bits 11 and 12 of mstatus
li x28, 1
slli x28, x28, 11
csrs mstatus, x28 # Set bits 11 and 12 of mstatus to 01, meaning
# the previous privilege mode is supervisor mode
auipc x28, 0 # Store the current program counter address in x28
addi x28, x28, 16 # x28 is now right after the mret instruction
csrw mepc, x28 # Set mepc to the value in x28
mret # On mret, we go back to the previous privilege mode in
# mstatus (S) and go to the next instruction.
ret # after going into supervisor mode, we need to return from this function
configPLIC:
# priority threshold = 0
li x5, 0xC200000
li x28, 0
sw x28, 0(x5)
# source 3 (GPIO) priority = 6
li x5, 0xC000000
li x28, 6
sw x28, 0x0C(x5)
# source 4 (UART) priority = 7
li x28, 7
sw x28, 0x10(x5)
# enable sources 3,4
li x5, 0x0C002000
li x28, 0b11000
sw x28, 0(x5)
ret
configGPIO:
# enable all inputs
li x5, 0x10060000
li x28, 0xFFFFFFFF
sw x28, 0x04(x5)
# enable all outputs
sw x28, 0x08(x5)
# enable all rising edge interrupts
sw x28, 0x18(x5)
# set MEIE
li x5, 0x800
csrs mie, x5
ret
stackTrapHandlerM:
# trap handler for when we use ecall to test the privilege mode stack.
# x28 holds the previous mstatus value
csrr x29, mstatus
li x5, 3
slli x5, x5, 11 # mask out MPP bits
jal checkBits # mpp should be 11
li x5, 1
slli x5, x5, 8 # mask out spp bits
jal checkBits # spp should be zero.
li x5, 1
slli x5, x5, 3 # mask out MIE bit
jal checkBits # MIE should be set to zero
li x5, 1
slli x5, x5, 7 # mask out MPIE bit
and x5, x29, x5
li x7, 1
slli x7, x7, 3 # mask out previous MIE bit
and x7, x7, x28
slli x7, x7, 4 # put the bits in the same place
xor x5, x7, x5 # check if theyre the same
sw x5, 0(x6) # should be all zeros.
addi x6, x6, 4
li x5, 1
slli x5, x5, 5 # mask out SPIE bit
and x5, x29, x5
li x7, 2 # mask out previous SIE bit
and x7, x7, x28
slli x7, x7, 4 # put the bits in the same place
xor x5, x7, x5 # check if theyre the same
sw x5, 0(x6) # should be all zeros.
addi x6, x6, 4
csrr x29, mepc
addi x29, x29, 4
csrw mepc, x29
mret
stackTrapHandlerS:
# trap handler for when we use ecall to test the privilege mode stack.
# x28 holds the previous sstatus value
csrr x29, sstatus
li x5, 1
slli x5, x5, 8 # mask out spp bit
jal checkBitsS # spp should be 1.
li x5, 1
slli x5, x5, 1 # mask out SIE bit
jal checkBitsS # SIE should be set to zero
li x5, 1
slli x5, x5, 5 # mask out SPIE bit
and x5, x29, x5
li x7, 2 # mask out previous SIE bit
and x7, x7, x28
slli x7, x7, 4 # put the bits in the same place
xor x5, x7, x5 # check if theyre the same
sw x5, 0(x6) # should be all zeros.
addi x6, x6, 4
# set return location to AFTER the ecall.
csrr x29, sepc
addi x29, x29, 4
csrw sepc, x29
sret
GPIOTrapHandler:
# several 'set low' reads to indicate we've handled the interrupt.
# 0x10: input_val
li x5, 0x10060000
lw x7, 0x00(x5)
# 0x14: output_val
lw x7, 0x0C(x5)
# 0x18: incoming rise_ip
lw x7, 0x1C(x5)
# 0x1C: serviced rise_ip = 0
sw x7, 0x1C(x5)
lw x7, 0x1C(x5)
# 0x20: incoming fall_ip
lw x7, 0x24(x5)
# 0x24: serviced fall_ip = 0
sw x7, 0x24(x5)
lw x7, 0x24(x5)
# 0x28: incoming high_ip
lw x7, 0x2C(x5)
# 0x2C: serviced high_ip = 0
sw x7, 0x2C(x5)
lw x7, 0x2C(x5)
# 0x30: incoming low_ip
lw x7, 0x34(x5)
# 0x34: serviced low_ip = 0
sw x7, 0x34(x5)
lw x7, 0x34(x5)
# check PLIC claim register
# (has the side effect of telling the PLIC that this interrupt is being handled)
li x5, 0x0C200004
lw x7, 0(x5)
# skip a lot of the GPIO handling because this test doesnt care about the actual input
# and receiving the value from GPIO, we just care about whther the interrupt happened.
li x7, 0x6410 # "gpio"
sw x7, 0(x6)
addi x6, x6, 4
# Signal to PLIC that the trap was handled.
li x5, 0x0C200004
li x7, 3
sw x7, 0(x5)
# reset GPIO, show interrupt was handled
li x5, 0x10060000
li x28, 0x00080000
sw x28, 0x1C(x5)
li x10, 0x76 # random nonzero number to break the bne x0 loop
mret
done:
RVMODEL_HALT
RVTEST_DATA_BEGIN
RVTEST_DATA_END
RVMODEL_DATA_BEGIN
# signature output
wally_signature:
.fill 16, 4, -1
#ifdef rvtest_mtrap_routine
mtrap_sigptr:
.fill 64*(XLEN/32),4,0xdeadbeef
#endif
#ifdef rvtest_gpr_save
gpr_save:
.fill 32*(XLEN/32),4,0xdeadbeef
#endif
RVMODEL_DATA_END

1455
tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-MTVEC.S
View File

File diff suppressed because it is too large Load Diff

3778
tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-MVENDORID.S
View File

File diff suppressed because it is too large Load Diff

1396
tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-SCAUSE.S
View File

File diff suppressed because it is too large Load Diff

1022
tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-STVEC.S
View File

File diff suppressed because it is too large Load Diff

459
tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-UCAUSE.S
View File

@ -1,459 +0,0 @@
///////////////////////////////////////////
// ../../../imperas-riscv-tests/riscv-test-suite/rv64p/src/WALLY-UCAUSE.S
// dottolia@hmc.edu
// Created 2021-04-20 15:11:17.438819//
// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
// Adapted from Imperas RISCV-TEST_SUITE
//
// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy,
// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software
// is furnished to do so, subject to the following conditions:
//
// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
//
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
///////////////////////////////////////////
#include "model_test.h"
#include "arch_test.h"
RVTEST_ISA("RV64I")
.section .text.init
.globl rvtest_entry_point
rvtest_entry_point:
RVMODEL_BOOT
# ---------------------------------------------------------------------------------------------
# address for test results
la x6, wally_signature
csrr x31, mtvec
li x30, 0
la x1, _j_m_trap
csrw mtvec, x1
la x1, _j_s_trap
csrw stvec, x1
j _j_t_begin
_j_m_trap:
csrrs x25, mcause, x0
csrrs x1, mepc, x0
addi x1, x1, 4
csrrw x0, mepc, x1
bnez x30, _j_all_end
mret
_j_s_trap:
csrrs x25, scause, x0
csrrs x1, sepc, x0
addi x1, x1, 4
csrrw x0, sepc, x1
sret
_j_t_begin:
li x1, 0b110000000000
csrrc x28, mstatus, x1
li x1, 0b0000000000000
csrrs x28, mstatus, x1
auipc x1, 0
addi x1, x1, 16 # x1 is now right after the mret instruction
csrw mepc, x1
mret
# We're now in u mode...
li x25, 0x7BAD
.fill 1, 4, 0
_jend0:
sd x25, 0(x6)
li x25, 0x7BAD
ebreak
_jend1:
sd x25, 8(x6)
li x25, 0x7BAD
lw x0, 11(x0)
_jend2:
sd x25, 16(x6)
li x25, 0x7BAD
sw x0, 11(x0)
_jend3:
sd x25, 24(x6)
li x25, 0x7BAD
ecall
_jend4:
sd x25, 32(x6)
li x25, 0x7BAD
.fill 1, 4, 0
_jend5:
sd x25, 40(x6)
li x25, 0x7BAD
ebreak
_jend6:
sd x25, 48(x6)
li x25, 0x7BAD
lw x0, 11(x0)
_jend7:
sd x25, 56(x6)
li x25, 0x7BAD
sw x0, 11(x0)
_jend8:
sd x25, 64(x6)
li x25, 0x7BAD
ecall
_jend9:
sd x25, 72(x6)
li x25, 0x7BAD
.fill 1, 4, 0
_jend10:
sd x25, 80(x6)
li x25, 0x7BAD
ebreak
_jend11:
sd x25, 88(x6)
li x25, 0x7BAD
lw x0, 11(x0)
_jend12:
sd x25, 96(x6)
li x25, 0x7BAD
sw x0, 11(x0)
_jend13:
sd x25, 104(x6)
li x25, 0x7BAD
ecall
_jend14:
sd x25, 112(x6)
li x25, 0x7BAD
.fill 1, 4, 0
_jend15:
sd x25, 120(x6)
li x25, 0x7BAD
ebreak
_jend16:
sd x25, 128(x6)
li x25, 0x7BAD
lw x0, 11(x0)
_jend17:
sd x25, 136(x6)
li x25, 0x7BAD
sw x0, 11(x0)
_jend18:
sd x25, 144(x6)
li x25, 0x7BAD
ecall
_jend19:
sd x25, 152(x6)
li x25, 0x7BAD
.fill 1, 4, 0
_jend20:
sd x25, 160(x6)
li x25, 0x7BAD
ebreak
_jend21:
sd x25, 168(x6)
li x25, 0x7BAD
lw x0, 11(x0)
_jend22:
sd x25, 176(x6)
li x25, 0x7BAD
sw x0, 11(x0)
_jend23:
sd x25, 184(x6)
li x25, 0x7BAD
ecall
_jend24:
sd x25, 192(x6)
li x25, 0x7BAD
.fill 1, 4, 0
_jend25:
sd x25, 200(x6)
li x25, 0x7BAD
ebreak
_jend26:
sd x25, 208(x6)
li x25, 0x7BAD
lw x0, 11(x0)
_jend27:
sd x25, 216(x6)
li x25, 0x7BAD
sw x0, 11(x0)
_jend28:
sd x25, 224(x6)
li x25, 0x7BAD
ecall
_jend29:
sd x25, 232(x6)
li x25, 0x7BAD
.fill 1, 4, 0
_jend30:
sd x25, 240(x6)
li x25, 0x7BAD
ebreak
_jend31:
sd x25, 248(x6)
li x25, 0x7BAD
lw x0, 11(x0)
_jend32:
sd x25, 256(x6)
li x25, 0x7BAD
sw x0, 11(x0)
_jend33:
sd x25, 264(x6)
li x25, 0x7BAD
ecall
_jend34:
sd x25, 272(x6)
li x25, 0x7BAD
.fill 1, 4, 0
_jend35:
sd x25, 280(x6)
li x25, 0x7BAD
ebreak
_jend36:
sd x25, 288(x6)
li x25, 0x7BAD
lw x0, 11(x0)
_jend37:
sd x25, 296(x6)
li x25, 0x7BAD
sw x0, 11(x0)
_jend38:
sd x25, 304(x6)
li x25, 0x7BAD
ecall
_jend39:
sd x25, 312(x6)
li x30, 1
ecall
_j_all_end:
csrw mtvec, x31
# ---------------------------------------------------------------------------------------------
RVMODEL_HALT
RVTEST_DATA_BEGIN
RVTEST_DATA_END
RVMODEL_DATA_BEGIN
# signature output
wally_signature:
.fill 40, 8, -1
#ifdef rvtest_mtrap_routine
mtrap_sigptr:
.fill 64*(XLEN/32),4,0xdeadbeef
#endif
#ifdef rvtest_gpr_save
gpr_save:
.fill 32*(XLEN/32),4,0xdeadbeef
#endif
RVMODEL_DATA_END

35
tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-scratch-01.S
View File

@ -1,35 +0,0 @@
///////////////////////////////////////////
//
// WALLY-scratch
//
// Author: Kip Macsai-Goren <kmacsaigoren@g.hmc.edu>
//
// Created 2022-02-20
//
// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
//
// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy,
// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software
// is furnished to do so, subject to the following conditions:
//
// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
//
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
///////////////////////////////////////////
#include "WALLY-TEST-LIB-64.h"
INIT_TESTS
TRAP_HANDLER m
// Test 5.3.2.3: Scratch registers test
WRITE_READ_CSR mscratch, 0x111 // check that mscratch is readable and writeable in machine mode
END_TESTS
TEST_STACK_AND_DATA

39
tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-sscratch-s-01.S
View File

@ -1,39 +0,0 @@
///////////////////////////////////////////
//
// WALLY-sscratch
//
// Author: Kip Macsai-Goren <kmacsaigoren@g.hmc.edu>
//
// Created 2022-02-20
//
// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
//
// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy,
// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software
// is furnished to do so, subject to the following conditions:
//
// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
//
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
///////////////////////////////////////////
#include "WALLY-TEST-LIB-64.h"
INIT_TESTS
TRAP_HANDLER m
// Test 5.3.2.3: Scratch registers test
WRITE_READ_CSR sscratch, 0x111 // check that sscratch is readable and writeable in machine mode
GOTO_S_MODE 0x0, 0x0
WRITE_READ_CSR sscratch, 0xAAA // check that sscratch is readable and writeable in supervisor mode
END_TESTS
TEST_STACK_AND_DATA