forked from Github_Repos/cvw
plots and synth runs
This commit is contained in:
Madeleine Masser-Frye
parent
1bf1a6d3a5
commit
b5b29ea705
@ -1,17 +0,0 @@
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GNU gdb (GDB) Red Hat Enterprise Linux 8.2-16.el8
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Copyright (C) 2018 Free Software Foundation, Inc.
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License GPLv3+: GNU GPL version 3 or later <http://gnu.org/licenses/gpl.html>
|
||||
This is free software: you are free to change and redistribute it.
|
||||
There is NO WARRANTY, to the extent permitted by law.
|
||||
Type "show copying" and "show warranty" for details.
|
||||
This GDB was configured as "x86_64-redhat-linux-gnu".
|
||||
Type "show configuration" for configuration details.
|
||||
For bug reporting instructions, please see:
|
||||
<http://www.gnu.org/software/gdb/bugs/>.
|
||||
Find the GDB manual and other documentation resources online at:
|
||||
<http://www.gnu.org/software/gdb/documentation/>.
|
||||
|
||||
For help, type "help".
|
||||
Type "apropos word" to search for commands related to "word".
|
||||
Attaching to process 12580
|
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(gdb) (gdb) (gdb) (gdb)
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@ -1,17 +0,0 @@
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GNU gdb (GDB) Red Hat Enterprise Linux 8.2-16.el8
|
||||
Copyright (C) 2018 Free Software Foundation, Inc.
|
||||
License GPLv3+: GNU GPL version 3 or later <http://gnu.org/licenses/gpl.html>
|
||||
This is free software: you are free to change and redistribute it.
|
||||
There is NO WARRANTY, to the extent permitted by law.
|
||||
Type "show copying" and "show warranty" for details.
|
||||
This GDB was configured as "x86_64-redhat-linux-gnu".
|
||||
Type "show configuration" for configuration details.
|
||||
For bug reporting instructions, please see:
|
||||
<http://www.gnu.org/software/gdb/bugs/>.
|
||||
Find the GDB manual and other documentation resources online at:
|
||||
<http://www.gnu.org/software/gdb/documentation/>.
|
||||
|
||||
For help, type "help".
|
||||
Type "apropos word" to search for commands related to "word".
|
||||
Attaching to process 32764
|
||||
(gdb) (gdb) (gdb) (gdb)
|
||||
@ -1,17 +0,0 @@
|
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GNU gdb (GDB) Red Hat Enterprise Linux 8.2-16.el8
|
||||
Copyright (C) 2018 Free Software Foundation, Inc.
|
||||
License GPLv3+: GNU GPL version 3 or later <http://gnu.org/licenses/gpl.html>
|
||||
This is free software: you are free to change and redistribute it.
|
||||
There is NO WARRANTY, to the extent permitted by law.
|
||||
Type "show copying" and "show warranty" for details.
|
||||
This GDB was configured as "x86_64-redhat-linux-gnu".
|
||||
Type "show configuration" for configuration details.
|
||||
For bug reporting instructions, please see:
|
||||
<http://www.gnu.org/software/gdb/bugs/>.
|
||||
Find the GDB manual and other documentation resources online at:
|
||||
<http://www.gnu.org/software/gdb/documentation/>.
|
||||
|
||||
For help, type "help".
|
||||
Type "apropos word" to search for commands related to "word".
|
||||
Attaching to process 52064
|
||||
(gdb) (gdb) (gdb) (gdb)
|
||||
@ -1,17 +0,0 @@
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GNU gdb (GDB) Red Hat Enterprise Linux 8.2-16.el8
|
||||
Copyright (C) 2018 Free Software Foundation, Inc.
|
||||
License GPLv3+: GNU GPL version 3 or later <http://gnu.org/licenses/gpl.html>
|
||||
This is free software: you are free to change and redistribute it.
|
||||
There is NO WARRANTY, to the extent permitted by law.
|
||||
Type "show copying" and "show warranty" for details.
|
||||
This GDB was configured as "x86_64-redhat-linux-gnu".
|
||||
Type "show configuration" for configuration details.
|
||||
For bug reporting instructions, please see:
|
||||
<http://www.gnu.org/software/gdb/bugs/>.
|
||||
Find the GDB manual and other documentation resources online at:
|
||||
<http://www.gnu.org/software/gdb/documentation/>.
|
||||
|
||||
For help, type "help".
|
||||
Type "apropos word" to search for commands related to "word".
|
||||
Attaching to process 55441
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(gdb) (gdb) (gdb) (gdb)
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@ -1,17 +0,0 @@
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GNU gdb (GDB) Red Hat Enterprise Linux 8.2-16.el8
|
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Copyright (C) 2018 Free Software Foundation, Inc.
|
||||
License GPLv3+: GNU GPL version 3 or later <http://gnu.org/licenses/gpl.html>
|
||||
This is free software: you are free to change and redistribute it.
|
||||
There is NO WARRANTY, to the extent permitted by law.
|
||||
Type "show copying" and "show warranty" for details.
|
||||
This GDB was configured as "x86_64-redhat-linux-gnu".
|
||||
Type "show configuration" for configuration details.
|
||||
For bug reporting instructions, please see:
|
||||
<http://www.gnu.org/software/gdb/bugs/>.
|
||||
Find the GDB manual and other documentation resources online at:
|
||||
<http://www.gnu.org/software/gdb/documentation/>.
|
||||
|
||||
For help, type "help".
|
||||
Type "apropos word" to search for commands related to "word".
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Attaching to process 57184
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(gdb) (gdb) (gdb) (gdb)
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@ -1,17 +0,0 @@
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GNU gdb (GDB) Red Hat Enterprise Linux 8.2-16.el8
|
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Copyright (C) 2018 Free Software Foundation, Inc.
|
||||
License GPLv3+: GNU GPL version 3 or later <http://gnu.org/licenses/gpl.html>
|
||||
This is free software: you are free to change and redistribute it.
|
||||
There is NO WARRANTY, to the extent permitted by law.
|
||||
Type "show copying" and "show warranty" for details.
|
||||
This GDB was configured as "x86_64-redhat-linux-gnu".
|
||||
Type "show configuration" for configuration details.
|
||||
For bug reporting instructions, please see:
|
||||
<http://www.gnu.org/software/gdb/bugs/>.
|
||||
Find the GDB manual and other documentation resources online at:
|
||||
<http://www.gnu.org/software/gdb/documentation/>.
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||||
|
||||
For help, type "help".
|
||||
Type "apropos word" to search for commands related to "word".
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Attaching to process 57185
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(gdb) (gdb) (gdb) (gdb)
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101
synthDC/bestSynths.csv
Normal file
101
synthDC/bestSynths.csv
Normal file
@ -0,0 +1,101 @@
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Module,Tech,Width,Target Freq,Delay,Area,L Power (nW),D energy (fJ)
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priorityencoder,sky90,8,7994,0.12495900000000001,60.760001,44.346,13.420596600000001
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priorityencoder,sky90,16,5753,0.16977,136.220003,77.243,21.255203999999996
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priorityencoder,sky90,32,4776,0.20887,379.260006,246.78,50.066139
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priorityencoder,sky90,64,4096,0.244022,794.780014,364.853,72.718556
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priorityencoder,sky90,128,3409,0.293333,1602.300031,610.009,126.13319000000001
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add,sky90,8,3652,0.27337,245.000005,139.276,101.69364
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add,sky90,16,2931,0.339912,623.280012,352.919,268.53048
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add,sky90,32,2420,0.413219,1330.840024,582.809,520.65594
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add,sky90,64,2139,0.467468,2781.240054,1050.0,939.143212
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add,sky90,128,1885,0.5304949999999999,6186.740118,2230.0,2147.974254999999
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csa,sky90,8,5984,0.166714,306.740006,227.761,164.046576
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csa,sky90,16,5984,0.165225,588.000011,322.135,321.1974
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csa,sky90,32,5740,0.166714,1160.320023,826.559,570.495308
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csa,sky90,64,5984,0.165225,2469.600048,1440.0,1354.3493250000001
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csa,sky90,128,5984,0.165225,4897.060095,2990.0,2649.0524250000003
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shiftleft,sky90,8,4321,0.23109,250.880004,181.951,70.25136
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shiftleft,sky90,16,3355,0.29804,666.400006,558.433,195.51424
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shiftleft,sky90,32,2500,0.39945200000000003,1400.420023,738.137,368.29474400000004
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shiftleft,sky90,64,2203,0.453859,3914.120062,2680.0,1144.632398
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shiftleft,sky90,128,1907,0.5242939999999999,9192.400136,6080.0,2900.3944079999997
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comparator,sky90,8,4829,0.206669,198.940004,136.459,48.567215
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comparator,sky90,16,4014,0.24886599999999998,355.740006,188.666,62.714231999999996
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comparator,sky90,32,3596,0.27763899999999997,697.760013,316.793,109.389766
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comparator,sky90,64,3129,0.319542,1372.980026,508.393,204.826422
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comparator,sky90,128,2682,0.37267500000000003,2836.120055,772.571,463.6077000000001
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flop,sky90,8,7708,0.11434399999999999,133.279999,129.629,341.2939712
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flop,sky90,16,7708,0.11434399999999999,266.5599975,259.258,682.4049919999999
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flop,sky90,32,7708,0.11434399999999999,533.119995,518.516,1364.69564
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flop,sky90,64,8396,0.114344,1066.23999,1040.0,2972.829656
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flop,sky90,128,8396,0.114344,2132.4799805,2070.0,5945.087592
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mux2,sky90,8,5280,0.188723,63.700001,23.506,19.4762136
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mux2,sky90,16,4815,0.202073,119.560002,32.354,37.7674437
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mux2,sky90,32,5000,0.19989700000000002,374.360008,259.372,136.72954800000002
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mux2,sky90,64,4060,0.245667,514.50001,165.954,163.614222
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mux2,sky90,128,4004,0.249748,1302.420025,767.078,466.52926399999996
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mux4,sky90,8,4655,0.214552,159.740002,86.462,42.0307368
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mux4,sky90,16,4452,0.223139,392.0,398.313,103.090218
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mux4,sky90,32,3802,0.262263,465.500009,150.568,139.26165300000002
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mux4,sky90,64,3699,0.269517,877.100017,304.149,274.90734
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mux4,sky90,128,3166,0.31572500000000003,1984.500039,725.267,569.5679000000001
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mux8,sky90,8,3577,0.27891699999999997,287.140006,116.648,60.831797699999996
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mux8,sky90,16,3419,0.29151,588.000006,280.193,150.71067
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mux8,sky90,32,3155,0.314651,1237.740008,639.983,323.14657700000004
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mux8,sky90,64,3020,0.330329,2207.940042,730.503,445.613821
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mux8,sky90,128,2666,0.37501399999999996,3761.240072,1460.0,854.281892
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mult,sky90,8,1310,0.7631560000000001,2194.220041,1440.0,1420.996472
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mult,sky90,16,997,1.002926,7519.540137,4940.0,6375.600582
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mult,sky90,32,763,1.310613,25200.700446,14900.0,24931.791099000002
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mult,sky90,64,632,1.5822660000000002,86011.661365,42600.0,88845.818166
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mult,sky90,128,524,1.9083759999999999,296198.144128,114000.0,273311.88559200004
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priorityencoder,tsmc28,8,31306,0.031913,8.316,34.836,1.7137280999999998
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priorityencoder,tsmc28,16,21202,0.047050999999999996,21.294,73.912,3.8158361
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priorityencoder,tsmc28,32,16453,0.06074,62.118,205.801,9.438996
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priorityencoder,tsmc28,64,13786,0.07244400000000001,137.088001,428.365,18.328332000000003
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priorityencoder,tsmc28,128,11439,0.087412,315.252,980.365,40.908816
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add,tsmc28,8,13787,0.072267,33.012,176.194,12.328750199999996
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add,tsmc28,16,11520,0.08680199999999999,90.972001,475.452,33.679176
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add,tsmc28,32,9810,0.101918,209.286002,1060.0,81.43248200000001
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add,tsmc28,64,8203,0.121869,392.616003,1800.0,142.34299200000004
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add,tsmc28,128,7210,0.138694,868.140006,4090.0,331.33996600000006
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csa,tsmc28,8,23865,0.040776,49.392,473.393,20.918088
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csa,tsmc28,16,23865,0.040776,98.783999,946.879,41.75462400000001
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csa,tsmc28,32,23865,0.040776,197.567999,1890.0,83.305368
|
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csa,tsmc28,64,23865,0.040776,395.135998,3790.0,166.52918400000001
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csa,tsmc28,128,23865,0.040776,790.271996,7570.0,333.099144
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shiftleft,tsmc28,8,15183,0.06578,48.384,333.876,15.517502
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shiftleft,tsmc28,16,11800,0.084718,130.788,613.549,33.717764
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shiftleft,tsmc28,32,9587,0.104304,384.803997,1940.0,101.800704
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shiftleft,tsmc28,64,8269,0.120883,967.427998,4980.0,272.8329309999999
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shiftleft,tsmc28,128,7023,0.14238299999999998,1836.953994,8670.0,566.541957
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comparator,tsmc28,8,17054,0.058548,32.256,160.477,8.752925999999999
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comparator,tsmc28,16,13709,0.07280299999999999,48.132,204.944,11.8523284
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comparator,tsmc28,32,12136,0.082381,146.16,623.674,35.506211
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comparator,tsmc28,64,10862,0.09205799999999999,291.312,1240.0,69.41173199999999
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comparator,tsmc28,128,9371,0.106711,558.432,2400.0,127.946489
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flop,tsmc28,8,19458,0.048892,15.12,157.268,51.8450768
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flop,tsmc28,16,19226,0.048892,30.24,314.578,102.39940480000001
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flop,tsmc28,32,20286,0.048892,60.4799995,629.157,216.053748
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flop,tsmc28,64,20286,0.048892,120.959999,1260.0,432.107496
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flop,tsmc28,128,20286,0.048892,241.919998,2520.0,864.1661
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mux2,tsmc28,8,29634,0.033745,16.758,114.564,5.436319499999999
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mux2,tsmc28,16,19150,0.052219,15.75,88.448,5.1592372
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mux2,tsmc28,32,17903,0.055855999999999996,32.130001,171.146,9.897683199999998
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mux2,tsmc28,64,18546,0.053857,90.846,517.414,27.359356000000002
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mux2,tsmc28,128,16594,0.060106,184.968,1150.0,58.603350000000006
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mux4,tsmc28,8,18130,0.055091999999999995,27.971999,133.963,8.0213952
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mux4,tsmc28,16,16440,0.060656,39.438,185.149,12.373824000000003
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mux4,tsmc28,32,15168,0.065805,69.174,324.969,23.229165
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mux4,tsmc28,64,13915,0.071806,137.465999,648.086,45.59681
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mux4,tsmc28,128,13089,0.07639599999999999,296.603997,1440.0,94.501852
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mux8,tsmc28,8,12885,0.07751,44.856,215.13,11.905536000000001
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mux8,tsmc28,16,12256,0.081543,121.841998,521.624,25.930674
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mux8,tsmc28,32,11695,0.085374,168.21,815.694,46.35808200000001
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mux8,tsmc28,64,11000,0.090793,304.037999,1490.0,81.895286
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mux8,tsmc28,128,10464,0.095475,664.775992,2850.0,153.04642500000003
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mult,tsmc28,8,5091,0.196425,516.222001,3840.0,342.95804999999996
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mult,tsmc28,16,3819,0.261843,1634.472002,11800.0,1455.3233939999998
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mult,tsmc28,32,2973,0.33635600000000004,5141.430011,36900.0,5416.340668
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mult,tsmc28,64,2390,0.41840900000000003,16045.092071,109000.0,18545.978925000003
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mult,tsmc28,128,1868,0.535328,44272.49428,262000.0,50011.412416
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@ -1,67 +0,0 @@
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CRTE_SNAPSHOT_START
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SECTION_CRTE_VERSION
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3.0
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SECTION_PID
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12580
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SECTION_POLLING_INTERVAL
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5
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SECTION_DATE_TIME
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Mon May 16 23:44:09 UTC 2022 (1652744649)
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SECTION_OS_VERSION
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osname: Linux
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hostname: tera
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arch: x86_64
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release_version: 5.4.157-1-pve
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SECTION_IPC_INFO
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------ Message Queues --------
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key msqid owner perms used-bytes messages
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------ Shared Memory Segments --------
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key shmid owner perms bytes nattch status
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0x00000000 15859713 nwhyte-agu 600 524288 2 dest
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0x00000000 360451 nwhyte-agu 600 524288 2 dest
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0x00000000 65540 kkim 600 134217728 2 dest
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0x00000000 557061 nwhyte-agu 600 67108864 2 dest
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0x00000000 6 harris 600 524288 2 dest
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0x00000000 7 harris 600 524288 2 dest
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0x00000000 5275656 harris 600 2097152 2 dest
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0x00000000 11993097 kkim 600 524288 2 dest
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0x00000000 15892490 kkim 600 524288 2 dest
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0x00000000 11 harris 600 524288 2 SECTION_ULIMIT
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core file size (blocks, -c) 0
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data seg size (kbytes, -d) unlimited
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scheduling priority (-e) 0
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file size (blocks, -f) unlimited
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pending signals (-i) 515072
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max locked memory (kbytes, -l) 64
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max memory size (kbytes, -m) unlimited
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open files (-n) 524288
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pipe size (512 bytes, -p) 8
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POSIX message queues (bytes, -q) 819200
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real-time priority (-r) 0
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stack size (kbytes, -s) unlimited
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cpu time (seconds, -t) unlimited
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max user processes (-u) 515072
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virtual memory (kbytes, -v) unlimited
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file locks (-x) unlimited
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SECTION_SYSCONF
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_SC_THREAD_SAFE_FUNCTIONS= 200809
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_SC_CLK_TCK= 100
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_SC_OPEN_MAX= 524288
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_SC_PAGE_SIZE= 4096
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_SC_ARG_MAX= 4611686018427387903
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_SC_CHILD_MAX= 515072
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_SC_LINE_MAX= 2048
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SECTION_FULL_COMMAND
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/cad/synopsys/SYN/linux64/syn/bin/common_shell_exec -64 -shell dc_shell -r /cad/synopsys/SYN -f scripts/synth.tcl
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SECTION_CPUINFO
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@ -1,67 +0,0 @@
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CRTE_SNAPSHOT_START
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SECTION_CRTE_VERSION
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3.0
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SECTION_PID
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32764
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SECTION_POLLING_INTERVAL
|
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5
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|
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SECTION_DATE_TIME
|
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Tue May 17 00:05:18 UTC 2022 (1652745918)
|
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SECTION_OS_VERSION
|
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osname: Linux
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hostname: tera
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arch: x86_64
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release_version: 5.4.157-1-pve
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SECTION_IPC_INFO
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------ Message Queues --------
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key msqid owner perms used-bytes messages
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||||
------ Shared Memory Segments --------
|
||||
key shmid owner perms bytes nattch status
|
||||
0x00000000 360451 nwhyte-agu 600 524288 2 dest
|
||||
0x00000000 65540 kkim 600 134217728 2 dest
|
||||
0x00000000 557061 nwhyte-agu 600 67108864 2 dest
|
||||
0x00000000 6 harris 600 524288 2 dest
|
||||
0x00000000 7 harris 600 524288 2 dest
|
||||
0x00000000 5275656 harris 600 2097152 2 dest
|
||||
0x00000000 11993097 kkim 600 524288 2 dest
|
||||
0x00000000 15892490 kkim 600 524288 2 dest
|
||||
0x00000000 11 harris 600 524288 2 dest
|
||||
0x00000000 15204364 harris 644 790528 3 SECTION_ULIMIT
|
||||
core file size (blocks, -c) 0
|
||||
data seg size (kbytes, -d) unlimited
|
||||
scheduling priority (-e) 0
|
||||
file size (blocks, -f) unlimited
|
||||
pending signals (-i) 515072
|
||||
max locked memory (kbytes, -l) 64
|
||||
max memory size (kbytes, -m) unlimited
|
||||
open files (-n) 524288
|
||||
pipe size (512 bytes, -p) 8
|
||||
POSIX message queues (bytes, -q) 819200
|
||||
real-time priority (-r) 0
|
||||
stack size (kbytes, -s) unlimited
|
||||
cpu time (seconds, -t) unlimited
|
||||
max user processes (-u) 515072
|
||||
virtual memory (kbytes, -v) unlimited
|
||||
file locks (-x) unlimited
|
||||
|
||||
SECTION_SYSCONF
|
||||
_SC_THREAD_SAFE_FUNCTIONS= 200809
|
||||
_SC_CLK_TCK= 100
|
||||
_SC_OPEN_MAX= 524288
|
||||
_SC_PAGE_SIZE= 4096
|
||||
_SC_ARG_MAX= 4611686018427387903
|
||||
_SC_CHILD_MAX= 515072
|
||||
_SC_LINE_MAX= 2048
|
||||
|
||||
SECTION_FULL_COMMAND
|
||||
/cad/synopsys/SYN/linux64/syn/bin/common_shell_exec -64 -shell dc_shell -r /cad/synopsys/SYN -f scripts/synth.tcl
|
||||
|
||||
SECTION_CPUINFO
|
||||
@ -1,67 +0,0 @@
|
||||
CRTE_SNAPSHOT_START
|
||||
|
||||
SECTION_CRTE_VERSION
|
||||
3.0
|
||||
|
||||
SECTION_PID
|
||||
52064
|
||||
|
||||
SECTION_POLLING_INTERVAL
|
||||
5
|
||||
|
||||
SECTION_DATE_TIME
|
||||
Thu May 12 21:44:48 UTC 2022 (1652391888)
|
||||
|
||||
SECTION_OS_VERSION
|
||||
osname: Linux
|
||||
hostname: tera
|
||||
arch: x86_64
|
||||
release_version: 5.4.157-1-pve
|
||||
|
||||
SECTION_IPC_INFO
|
||||
|
||||
------ Message Queues --------
|
||||
key msqid owner perms used-bytes messages
|
||||
|
||||
------ Shared Memory Segments --------
|
||||
key shmid owner perms bytes nattch status
|
||||
0x00000000 360451 nwhyte-agu 600 524288 2 dest
|
||||
0x00000000 65540 kkim 600 134217728 2 dest
|
||||
0x00000000 557061 nwhyte-agu 600 67108864 2 dest
|
||||
0x00000000 6 harris 600 524288 2 dest
|
||||
0x00000000 7 harris 600 524288 2 dest
|
||||
0x00000000 5275656 harris 600 2097152 2 dest
|
||||
0x00000000 11993097 kkim 600 524288 2 dest
|
||||
0x00000000 11 harris 600 524288 2 dest
|
||||
0x00000000 15204364 harris 644 790528 2 dest
|
||||
0x00000000 7372813 chuang 600 524288 2 SECTION_ULIMIT
|
||||
core file size (blocks, -c) 0
|
||||
data seg size (kbytes, -d) unlimited
|
||||
scheduling priority (-e) 0
|
||||
file size (blocks, -f) unlimited
|
||||
pending signals (-i) 515072
|
||||
max locked memory (kbytes, -l) 64
|
||||
max memory size (kbytes, -m) unlimited
|
||||
open files (-n) 524288
|
||||
pipe size (512 bytes, -p) 8
|
||||
POSIX message queues (bytes, -q) 819200
|
||||
real-time priority (-r) 0
|
||||
stack size (kbytes, -s) unlimited
|
||||
cpu time (seconds, -t) unlimited
|
||||
max user processes (-u) 515072
|
||||
virtual memory (kbytes, -v) unlimited
|
||||
file locks (-x) unlimited
|
||||
|
||||
SECTION_SYSCONF
|
||||
_SC_THREAD_SAFE_FUNCTIONS= 200809
|
||||
_SC_CLK_TCK= 100
|
||||
_SC_OPEN_MAX= 524288
|
||||
_SC_PAGE_SIZE= 4096
|
||||
_SC_ARG_MAX= 4611686018427387903
|
||||
_SC_CHILD_MAX= 515072
|
||||
_SC_LINE_MAX= 2048
|
||||
|
||||
SECTION_FULL_COMMAND
|
||||
/cad/synopsys/SYN/linux64/syn/bin/common_shell_exec -64 -shell dc_shell -r /cad/synopsys/SYN -f scripts/synth.tcl
|
||||
|
||||
SECTION_CPUINFO
|
||||
@ -1,67 +0,0 @@
|
||||
CRTE_SNAPSHOT_START
|
||||
|
||||
SECTION_CRTE_VERSION
|
||||
3.0
|
||||
|
||||
SECTION_PID
|
||||
55441
|
||||
|
||||
SECTION_POLLING_INTERVAL
|
||||
5
|
||||
|
||||
SECTION_DATE_TIME
|
||||
Thu May 12 21:47:47 UTC 2022 (1652392067)
|
||||
|
||||
SECTION_OS_VERSION
|
||||
osname: Linux
|
||||
hostname: tera
|
||||
arch: x86_64
|
||||
release_version: 5.4.157-1-pve
|
||||
|
||||
SECTION_IPC_INFO
|
||||
|
||||
------ Message Queues --------
|
||||
key msqid owner perms used-bytes messages
|
||||
|
||||
------ Shared Memory Segments --------
|
||||
key shmid owner perms bytes nattch status
|
||||
0x00000000 360451 nwhyte-agu 600 524288 2 dest
|
||||
0x00000000 65540 kkim 600 134217728 2 dest
|
||||
0x00000000 557061 nwhyte-agu 600 67108864 2 dest
|
||||
0x00000000 6 harris 600 524288 2 dest
|
||||
0x00000000 7 harris 600 524288 2 dest
|
||||
0x00000000 5275656 harris 600 2097152 2 dest
|
||||
0x00000000 11993097 kkim 600 524288 2 dest
|
||||
0x00000000 11 harris 600 524288 2 dest
|
||||
0x00000000 15204364 harris 644 790528 2 dest
|
||||
0x00000000 7372813 chuang 600 524288 2 SECTION_ULIMIT
|
||||
core file size (blocks, -c) 0
|
||||
data seg size (kbytes, -d) unlimited
|
||||
scheduling priority (-e) 0
|
||||
file size (blocks, -f) unlimited
|
||||
pending signals (-i) 515072
|
||||
max locked memory (kbytes, -l) 64
|
||||
max memory size (kbytes, -m) unlimited
|
||||
open files (-n) 524288
|
||||
pipe size (512 bytes, -p) 8
|
||||
POSIX message queues (bytes, -q) 819200
|
||||
real-time priority (-r) 0
|
||||
stack size (kbytes, -s) unlimited
|
||||
cpu time (seconds, -t) unlimited
|
||||
max user processes (-u) 515072
|
||||
virtual memory (kbytes, -v) unlimited
|
||||
file locks (-x) unlimited
|
||||
|
||||
SECTION_SYSCONF
|
||||
_SC_THREAD_SAFE_FUNCTIONS= 200809
|
||||
_SC_CLK_TCK= 100
|
||||
_SC_OPEN_MAX= 524288
|
||||
_SC_PAGE_SIZE= 4096
|
||||
_SC_ARG_MAX= 4611686018427387903
|
||||
_SC_CHILD_MAX= 515072
|
||||
_SC_LINE_MAX= 2048
|
||||
|
||||
SECTION_FULL_COMMAND
|
||||
/cad/synopsys/SYN/linux64/syn/bin/common_shell_exec -64 -shell dc_shell -r /cad/synopsys/SYN -f scripts/synth.tcl
|
||||
|
||||
SECTION_CPUINFO
|
||||
@ -1,67 +0,0 @@
|
||||
CRTE_SNAPSHOT_START
|
||||
|
||||
SECTION_CRTE_VERSION
|
||||
3.0
|
||||
|
||||
SECTION_PID
|
||||
57184
|
||||
|
||||
SECTION_POLLING_INTERVAL
|
||||
5
|
||||
|
||||
SECTION_DATE_TIME
|
||||
Mon May 16 22:54:26 UTC 2022 (1652741666)
|
||||
|
||||
SECTION_OS_VERSION
|
||||
osname: Linux
|
||||
hostname: tera
|
||||
arch: x86_64
|
||||
release_version: 5.4.157-1-pve
|
||||
|
||||
SECTION_IPC_INFO
|
||||
|
||||
------ Message Queues --------
|
||||
key msqid owner perms used-bytes messages
|
||||
|
||||
------ Shared Memory Segments --------
|
||||
key shmid owner perms bytes nattch status
|
||||
0x00000000 15859713 nwhyte-agu 600 524288 2 dest
|
||||
0x00000000 360451 nwhyte-agu 600 524288 2 dest
|
||||
0x00000000 65540 kkim 600 134217728 2 dest
|
||||
0x00000000 557061 nwhyte-agu 600 67108864 2 dest
|
||||
0x00000000 6 harris 600 524288 2 dest
|
||||
0x00000000 7 harris 600 524288 2 dest
|
||||
0x00000000 5275656 harris 600 2097152 2 dest
|
||||
0x00000000 11993097 kkim 600 524288 2 dest
|
||||
0x00000000 15892490 kkim 600 524288 2 dest
|
||||
0x00000000 11 harris 600 524288 2 SECTION_ULIMIT
|
||||
core file size (blocks, -c) 0
|
||||
data seg size (kbytes, -d) unlimited
|
||||
scheduling priority (-e) 0
|
||||
file size (blocks, -f) unlimited
|
||||
pending signals (-i) 515072
|
||||
max locked memory (kbytes, -l) 64
|
||||
max memory size (kbytes, -m) unlimited
|
||||
open files (-n) 524288
|
||||
pipe size (512 bytes, -p) 8
|
||||
POSIX message queues (bytes, -q) 819200
|
||||
real-time priority (-r) 0
|
||||
stack size (kbytes, -s) unlimited
|
||||
cpu time (seconds, -t) unlimited
|
||||
max user processes (-u) 515072
|
||||
virtual memory (kbytes, -v) unlimited
|
||||
file locks (-x) unlimited
|
||||
|
||||
SECTION_SYSCONF
|
||||
_SC_THREAD_SAFE_FUNCTIONS= 200809
|
||||
_SC_CLK_TCK= 100
|
||||
_SC_OPEN_MAX= 524288
|
||||
_SC_PAGE_SIZE= 4096
|
||||
_SC_ARG_MAX= 4611686018427387903
|
||||
_SC_CHILD_MAX= 515072
|
||||
_SC_LINE_MAX= 2048
|
||||
|
||||
SECTION_FULL_COMMAND
|
||||
/cad/synopsys/SYN/linux64/syn/bin/common_shell_exec -64 -shell dc_shell -r /cad/synopsys/SYN -f scripts/synth.tcl
|
||||
|
||||
SECTION_CPUINFO
|
||||
@ -1,67 +0,0 @@
|
||||
CRTE_SNAPSHOT_START
|
||||
|
||||
SECTION_CRTE_VERSION
|
||||
3.0
|
||||
|
||||
SECTION_PID
|
||||
57185
|
||||
|
||||
SECTION_POLLING_INTERVAL
|
||||
5
|
||||
|
||||
SECTION_DATE_TIME
|
||||
Mon May 16 22:54:26 UTC 2022 (1652741666)
|
||||
|
||||
SECTION_OS_VERSION
|
||||
osname: Linux
|
||||
hostname: tera
|
||||
arch: x86_64
|
||||
release_version: 5.4.157-1-pve
|
||||
|
||||
SECTION_IPC_INFO
|
||||
|
||||
------ Message Queues --------
|
||||
key msqid owner perms used-bytes messages
|
||||
|
||||
------ Shared Memory Segments --------
|
||||
key shmid owner perms bytes nattch status
|
||||
0x00000000 15859713 nwhyte-agu 600 524288 2 dest
|
||||
0x00000000 360451 nwhyte-agu 600 524288 2 dest
|
||||
0x00000000 65540 kkim 600 134217728 2 dest
|
||||
0x00000000 557061 nwhyte-agu 600 67108864 2 dest
|
||||
0x00000000 6 harris 600 524288 2 dest
|
||||
0x00000000 7 harris 600 524288 2 dest
|
||||
0x00000000 5275656 harris 600 2097152 2 dest
|
||||
0x00000000 11993097 kkim 600 524288 2 dest
|
||||
0x00000000 15892490 kkim 600 524288 2 dest
|
||||
0x00000000 11 harris 600 524288 2 SECTION_ULIMIT
|
||||
core file size (blocks, -c) 0
|
||||
data seg size (kbytes, -d) unlimited
|
||||
scheduling priority (-e) 0
|
||||
file size (blocks, -f) unlimited
|
||||
pending signals (-i) 515072
|
||||
max locked memory (kbytes, -l) 64
|
||||
max memory size (kbytes, -m) unlimited
|
||||
open files (-n) 524288
|
||||
pipe size (512 bytes, -p) 8
|
||||
POSIX message queues (bytes, -q) 819200
|
||||
real-time priority (-r) 0
|
||||
stack size (kbytes, -s) unlimited
|
||||
cpu time (seconds, -t) unlimited
|
||||
max user processes (-u) 515072
|
||||
virtual memory (kbytes, -v) unlimited
|
||||
file locks (-x) unlimited
|
||||
|
||||
SECTION_SYSCONF
|
||||
_SC_THREAD_SAFE_FUNCTIONS= 200809
|
||||
_SC_CLK_TCK= 100
|
||||
_SC_OPEN_MAX= 524288
|
||||
_SC_PAGE_SIZE= 4096
|
||||
_SC_ARG_MAX= 4611686018427387903
|
||||
_SC_CHILD_MAX= 515072
|
||||
_SC_LINE_MAX= 2048
|
||||
|
||||
SECTION_FULL_COMMAND
|
||||
/cad/synopsys/SYN/linux64/syn/bin/common_shell_exec -64 -shell dc_shell -r /cad/synopsys/SYN -f scripts/synth.tcl
|
||||
|
||||
SECTION_CPUINFO
|
||||
@ -1,998 +0,0 @@
|
||||
|
||||
Design Compiler Graphical
|
||||
DC Ultra (TM)
|
||||
DFTMAX (TM)
|
||||
Power Compiler (TM)
|
||||
DesignWare (R)
|
||||
DC Expert (TM)
|
||||
Design Vision (TM)
|
||||
HDL Compiler (TM)
|
||||
VHDL Compiler (TM)
|
||||
DFT Compiler
|
||||
Design Compiler(R)
|
||||
|
||||
Version S-2021.06-SP4 for linux64 - Nov 23, 2021
|
||||
|
||||
Copyright (c) 1988 - 2021 Synopsys, Inc.
|
||||
This software and the associated documentation are proprietary to Synopsys,
|
||||
Inc. This software may only be used in accordance with the terms and conditions
|
||||
of a written license agreement with Synopsys, Inc. All other use, reproduction,
|
||||
or distribution of this software is strictly prohibited. Licensed Products
|
||||
communicate with Synopsys servers for the purpose of providing software
|
||||
updates, detecting software piracy and verifying that customers are using
|
||||
Licensed Products in conformity with the applicable License Key for such
|
||||
Licensed Products. Synopsys will use information gathered in connection with
|
||||
this process to deliver software updates and pursue software pirates and
|
||||
infringers.
|
||||
|
||||
Inclusivity & Diversity - Visit SolvNetPlus to read the "Synopsys Statement on
|
||||
Inclusivity and Diversity" (Refer to article 000036315 at
|
||||
https://solvnetplus.synopsys.com)
|
||||
Initializing...
|
||||
#
|
||||
# Synthesis Synopsys Flow
|
||||
# james.stine@okstate.edu 27 Sep 2015
|
||||
#
|
||||
# Ignore unnecessary warnings:
|
||||
# intraassignment delays for nonblocking assignments are ignored
|
||||
suppress_message {VER-130}
|
||||
# statements in initial blocks are ignored
|
||||
suppress_message {VER-281}
|
||||
suppress_message {VER-173}
|
||||
# Enable Multicore
|
||||
set_host_options -max_cores $::env(MAXCORES)
|
||||
1
|
||||
# get outputDir from environment (Makefile)
|
||||
set outputDir $::env(OUTPUTDIR)
|
||||
runs/wallypipelinedcore_rv32e_sky90 nm_500_MHz_2022-03-22-20-43_2947df5b
|
||||
set cfgName $::env(CONFIG)
|
||||
rv32e
|
||||
# Config
|
||||
set hdl_src "../pipelined/src"
|
||||
../pipelined/src
|
||||
set cfg "${hdl_src}/../config/${cfgName}/wally-config.vh"
|
||||
../pipelined/src/../config/rv32e/wally-config.vh
|
||||
set saifpower $::env(SAIFPOWER)
|
||||
0
|
||||
set maxopt $::env(MAXOPT)
|
||||
0
|
||||
eval file copy -force ${cfg} {hdl/}
|
||||
eval file copy -force ${cfg} $outputDir
|
||||
eval file copy -force [glob ${hdl_src}/../config/shared/*.vh] {hdl/}
|
||||
eval file copy -force [glob ${hdl_src}/*/*.sv] {hdl/}
|
||||
eval file copy -force [glob ${hdl_src}/*/flop/*.sv] {hdl/}
|
||||
# Enables name mapping
|
||||
if { $saifpower == 1 } {
|
||||
saif_map -start
|
||||
}
|
||||
# Verilog files
|
||||
set my_verilog_files [glob hdl/*]
|
||||
hdl/gpio.sv hdl/cla64.sv hdl/cvtfp.sv hdl/flopenrc.sv hdl/csrm.sv hdl/adrdec.sv hdl/fpdiv.sv hdl/convert_inputs.sv hdl/forward.sv hdl/fpdiv_pipe.sv hdl/flopenl.sv hdl/unpacking.sv hdl/tlbcontrol.sv hdl/bpred.sv hdl/pmachecker.sv hdl/satCounter2.sv hdl/csr.sv hdl/fsm_fpdiv_pipe.sv hdl/prioritythermometer.sv hdl/mmu.sv hdl/csrn.sv hdl/ahblite.sv hdl/wally-config.vh hdl/wally-shared.vh hdl/cachereplacementpolicy.sv hdl/privileged.sv hdl/tlbmixer.sv hdl/privdec.sv hdl/or_rows.sv hdl/fctrl.sv hdl/sram1p1rw.sv hdl/unpack.sv hdl/decompress.sv hdl/extend.sv hdl/wally-constants.vh hdl/muldiv.sv hdl/tlbcamline.sv hdl/tlbramline.sv hdl/fcvtint.sv hdl/fcvtfp.sv hdl/regfile.sv hdl/sbtm_a0.sv hdl/subwordwrite.sv hdl/flopen.sv hdl/alu.sv hdl/cla12.sv hdl/dtim.sv hdl/csrsr.sv hdl/datapath.sv hdl/mux.sv hdl/adderparts.sv hdl/sbtm_a1.sv hdl/simpleram.sv hdl/sbtm_a3.sv hdl/busfsm.sv hdl/cachefsm.sv hdl/floprc.sv hdl/ieu.sv hdl/wallypipelinedcore.sv hdl/fsm_fpdiv.sv hdl/pmpadrdec.sv hdl/rounder_denorm.sv hdl/uncore.sv hdl/localHistoryPredictor.sv hdl/mul.sv hdl/clint.sv hdl/divconv_pipe.sv hdl/adder.sv hdl/tlb.sv hdl/uart.sv hdl/twoBitPredictor.sv hdl/sbtm_a2.sv hdl/csri.sv hdl/cacheway.sv hdl/amoalu.sv hdl/plic.sv hdl/interlockfsm.sv hdl/hptw.sv hdl/RAsPredictor.sv hdl/priorityonehot.sv hdl/fpudivsqrtrecur.sv hdl/synchronizer.sv hdl/faddcvt.sv hdl/fma16.sv hdl/intdivrestoringstep.sv hdl/ifu.sv hdl/redundantmul.sv hdl/pmpchecker.sv hdl/fclassify.sv hdl/tlbcam.sv hdl/fsgn.sv hdl/adrdecs.sv hdl/shifter.sv hdl/fma.sv hdl/wallypipelinedsoc.sv hdl/counter.sv hdl/rounder_div.sv hdl/trap.sv hdl/clockgater.sv hdl/SRAM2P1R1W.sv hdl/tlbram.sv hdl/neg.sv hdl/csrc.sv hdl/csru.sv hdl/lzd_denorm.sv hdl/comparator.sv hdl/fcvt.sv hdl/cla52.sv hdl/divconv.sv hdl/busdp.sv hdl/subcachelineread.sv hdl/subwordread.sv hdl/cache.sv hdl/exception_div.sv hdl/arrs.sv hdl/uartPC16550D.sv hdl/fhazard.sv hdl/fcmp.sv hdl/sbtm_div.sv hdl/decoder.sv hdl/controller.sv hdl/sbtm_sqrt.sv hdl/intdivrestoring.sv hdl/spillsupport.sv hdl/convert_inputs_div.sv hdl/swbytemask.sv hdl/flopr.sv hdl/lsuvirtmen.sv hdl/tlblru.sv hdl/onehotdecoder.sv hdl/fpudivsqrtrecurcore.sv hdl/flop.sv hdl/globalHistoryPredictor.sv hdl/fregfile.sv hdl/fpu.sv hdl/csrs.sv hdl/flopens.sv hdl/atomic.sv hdl/lsu.sv hdl/shifter_denorm.sv hdl/gsharePredictor.sv hdl/ram.sv hdl/hazard.sv hdl/BTBPredictor.sv hdl/flopenr.sv hdl/lrsc.sv hdl/exception.sv
|
||||
# Set toplevel
|
||||
set my_toplevel $::env(DESIGN)
|
||||
wallypipelinedcore
|
||||
# Set number of significant digits
|
||||
set report_default_significant_digits 6
|
||||
6
|
||||
# V(HDL) Unconnectoed Pins Output
|
||||
set verilogout_show_unconnected_pins "true"
|
||||
true
|
||||
set vhdlout_show_unconnected_pins "true"
|
||||
true
|
||||
# Due to parameterized Verilog must use analyze/elaborate and not
|
||||
# read_verilog/vhdl (change to pull in Verilog and/or VHDL)
|
||||
#
|
||||
define_design_lib WORK -path ./WORK
|
||||
1
|
||||
analyze -f sverilog -lib WORK $my_verilog_files
|
||||
Running PRESTO HDLC
|
||||
Compiling source file ./hdl/gpio.sv
|
||||
Opening include file ./hdl/wally-config.vh
|
||||
Opening include file ./hdl/wally-shared.vh
|
||||
Opening include file ./hdl/wally-constants.vh
|
||||
Compiling source file ./hdl/cla64.sv
|
||||
Compiling source file ./hdl/cvtfp.sv
|
||||
Opening include file ./hdl/wally-config.vh
|
||||
Opening include file ./hdl/wally-shared.vh
|
||||
Opening include file ./hdl/wally-constants.vh
|
||||
Compiling source file ./hdl/flopenrc.sv
|
||||
Opening include file ./hdl/wally-config.vh
|
||||
Opening include file ./hdl/wally-shared.vh
|
||||
Opening include file ./hdl/wally-constants.vh
|
||||
Compiling source file ./hdl/csrm.sv
|
||||
Opening include file ./hdl/wally-config.vh
|
||||
Opening include file ./hdl/wally-shared.vh
|
||||
Opening include file ./hdl/wally-constants.vh
|
||||
Compiling source file ./hdl/adrdec.sv
|
||||
Opening include file ./hdl/wally-config.vh
|
||||
Opening include file ./hdl/wally-shared.vh
|
||||
Opening include file ./hdl/wally-constants.vh
|
||||
Compiling source file ./hdl/fpdiv.sv
|
||||
Compiling source file ./hdl/convert_inputs.sv
|
||||
Compiling source file ./hdl/forward.sv
|
||||
Opening include file ./hdl/wally-config.vh
|
||||
Opening include file ./hdl/wally-shared.vh
|
||||
Opening include file ./hdl/wally-constants.vh
|
||||
Compiling source file ./hdl/fpdiv_pipe.sv
|
||||
Compiling source file ./hdl/flopenl.sv
|
||||
Opening include file ./hdl/wally-config.vh
|
||||
Opening include file ./hdl/wally-shared.vh
|
||||
Opening include file ./hdl/wally-constants.vh
|
||||
Compiling source file ./hdl/unpacking.sv
|
||||
Opening include file ./hdl/wally-config.vh
|
||||
Opening include file ./hdl/wally-shared.vh
|
||||
Opening include file ./hdl/wally-constants.vh
|
||||
Compiling source file ./hdl/tlbcontrol.sv
|
||||
Opening include file ./hdl/wally-config.vh
|
||||
Opening include file ./hdl/wally-shared.vh
|
||||
Opening include file ./hdl/wally-constants.vh
|
||||
Compiling source file ./hdl/bpred.sv
|
||||
Opening include file ./hdl/wally-config.vh
|
||||
Opening include file ./hdl/wally-shared.vh
|
||||
Opening include file ./hdl/wally-constants.vh
|
||||
Compiling source file ./hdl/pmachecker.sv
|
||||
Opening include file ./hdl/wally-config.vh
|
||||
Opening include file ./hdl/wally-shared.vh
|
||||
Opening include file ./hdl/wally-constants.vh
|
||||
Compiling source file ./hdl/satCounter2.sv
|
||||
Opening include file ./hdl/wally-config.vh
|
||||
Opening include file ./hdl/wally-shared.vh
|
||||
Opening include file ./hdl/wally-constants.vh
|
||||
Compiling source file ./hdl/csr.sv
|
||||
Opening include file ./hdl/wally-config.vh
|
||||
Opening include file ./hdl/wally-shared.vh
|
||||
Opening include file ./hdl/wally-constants.vh
|
||||
Compiling source file ./hdl/fsm_fpdiv_pipe.sv
|
||||
Compiling source file ./hdl/prioritythermometer.sv
|
||||
Opening include file ./hdl/wally-config.vh
|
||||
Opening include file ./hdl/wally-shared.vh
|
||||
Opening include file ./hdl/wally-constants.vh
|
||||
Compiling source file ./hdl/mmu.sv
|
||||
Opening include file ./hdl/wally-config.vh
|
||||
Opening include file ./hdl/wally-shared.vh
|
||||
Opening include file ./hdl/wally-constants.vh
|
||||
Compiling source file ./hdl/csrn.sv
|
||||
Opening include file ./hdl/wally-config.vh
|
||||
Opening include file ./hdl/wally-shared.vh
|
||||
Opening include file ./hdl/wally-constants.vh
|
||||
Compiling source file ./hdl/ahblite.sv
|
||||
Opening include file ./hdl/wally-config.vh
|
||||
Opening include file ./hdl/wally-shared.vh
|
||||
Opening include file ./hdl/wally-constants.vh
|
||||
Compiling source file ./hdl/wally-config.vh
|
||||
Opening include file ./hdl/wally-shared.vh
|
||||
Opening include file ./hdl/wally-constants.vh
|
||||
Compiling source file ./hdl/wally-shared.vh
|
||||
Opening include file ./hdl/wally-constants.vh
|
||||
Compiling source file ./hdl/cachereplacementpolicy.sv
|
||||
Opening include file ./hdl/wally-config.vh
|
||||
Opening include file ./hdl/wally-shared.vh
|
||||
Opening include file ./hdl/wally-constants.vh
|
||||
Compiling source file ./hdl/privileged.sv
|
||||
Opening include file ./hdl/wally-config.vh
|
||||
Opening include file ./hdl/wally-shared.vh
|
||||
Opening include file ./hdl/wally-constants.vh
|
||||
Compiling source file ./hdl/tlbmixer.sv
|
||||
Opening include file ./hdl/wally-config.vh
|
||||
Opening include file ./hdl/wally-shared.vh
|
||||
Opening include file ./hdl/wally-constants.vh
|
||||
Compiling source file ./hdl/privdec.sv
|
||||
Opening include file ./hdl/wally-config.vh
|
||||
Opening include file ./hdl/wally-shared.vh
|
||||
Opening include file ./hdl/wally-constants.vh
|
||||
Compiling source file ./hdl/or_rows.sv
|
||||
Opening include file ./hdl/wally-config.vh
|
||||
Opening include file ./hdl/wally-shared.vh
|
||||
Opening include file ./hdl/wally-constants.vh
|
||||
Compiling source file ./hdl/fctrl.sv
|
||||
Compiling source file ./hdl/sram1p1rw.sv
|
||||
Compiling source file ./hdl/unpack.sv
|
||||
Opening include file ./hdl/wally-config.vh
|
||||
Opening include file ./hdl/wally-shared.vh
|
||||
Opening include file ./hdl/wally-constants.vh
|
||||
Compiling source file ./hdl/decompress.sv
|
||||
Opening include file ./hdl/wally-config.vh
|
||||
Opening include file ./hdl/wally-shared.vh
|
||||
Opening include file ./hdl/wally-constants.vh
|
||||
Error: ./hdl/unpack.sv:100: Procedural-continuous assignments are not supported by synthesis. (VER-966)
|
||||
Error: ./hdl/unpack.sv:101: Procedural-continuous assignments are not supported by synthesis. (VER-966)
|
||||
Error: ./hdl/unpack.sv:102: Procedural-continuous assignments are not supported by synthesis. (VER-966)
|
||||
Error: ./hdl/unpack.sv:104: Procedural-continuous assignments are not supported by synthesis. (VER-966)
|
||||
Error: ./hdl/unpack.sv:105: Procedural-continuous assignments are not supported by synthesis. (VER-966)
|
||||
Error: ./hdl/unpack.sv:106: Procedural-continuous assignments are not supported by synthesis. (VER-966)
|
||||
Error: ./hdl/unpack.sv:108: Procedural-continuous assignments are not supported by synthesis. (VER-966)
|
||||
Error: ./hdl/unpack.sv:109: Procedural-continuous assignments are not supported by synthesis. (VER-966)
|
||||
Error: ./hdl/unpack.sv:110: Procedural-continuous assignments are not supported by synthesis. (VER-966)
|
||||
Error: ./hdl/unpack.sv:112: Procedural-continuous assignments are not supported by synthesis. (VER-966)
|
||||
Error: ./hdl/unpack.sv:113: Procedural-continuous assignments are not supported by synthesis. (VER-966)
|
||||
Error: ./hdl/unpack.sv:114: Procedural-continuous assignments are not supported by synthesis. (VER-966)
|
||||
Error: ./hdl/unpack.sv:116: Procedural-continuous assignments are not supported by synthesis. (VER-966)
|
||||
Error: ./hdl/unpack.sv:117: Procedural-continuous assignments are not supported by synthesis. (VER-966)
|
||||
Error: ./hdl/unpack.sv:118: Procedural-continuous assignments are not supported by synthesis. (VER-966)
|
||||
Error: ./hdl/unpack.sv:121: Procedural-continuous assignments are not supported by synthesis. (VER-966)
|
||||
Error: ./hdl/unpack.sv:122: Procedural-continuous assignments are not supported by synthesis. (VER-966)
|
||||
Error: ./hdl/unpack.sv:123: Procedural-continuous assignments are not supported by synthesis. (VER-966)
|
||||
Error: ./hdl/unpack.sv:132: Procedural-continuous assignments are not supported by synthesis. (VER-966)
|
||||
Error: ./hdl/unpack.sv:133: Procedural-continuous assignments are not supported by synthesis. (VER-966)
|
||||
Error: Too many errors; can't continue. (VER-40)
|
||||
*** Presto compilation terminated with 21 errors. ***
|
||||
Loading db file '/cad/synopsys/SYN/libraries/syn/dw_foundation.sldb'
|
||||
0
|
||||
elaborate $my_toplevel -lib WORK
|
||||
Loading db file '/cad/synopsys/SYN/libraries/syn/gtech.db'
|
||||
Loading db file '/cad/synopsys/SYN/libraries/syn/standard.sldb'
|
||||
Loading link library 'gtech'
|
||||
Running PRESTO HDLC
|
||||
Presto compilation completed successfully. (wallypipelinedcore)
|
||||
Elaborated 1 design.
|
||||
Current design is now 'wallypipelinedcore'.
|
||||
Information: Building the design 'ifu'. (HDL-193)
|
||||
Presto compilation completed successfully. (ifu)
|
||||
Information: Building the design 'ieu'. (HDL-193)
|
||||
Presto compilation completed successfully. (ieu)
|
||||
Information: Building the design 'lsu'. (HDL-193)
|
||||
Presto compilation completed successfully. (lsu)
|
||||
Information: Building the design 'ahblite'. (HDL-193)
|
||||
Warning: ./hdl/ahblite.sv:102: DEFAULT branch of CASE statement cannot be reached. (ELAB-311)
|
||||
|
||||
Statistics for case statements in always block at line 101 in file
|
||||
'./hdl/ahblite.sv'
|
||||
===============================================
|
||||
| Line | full/ parallel |
|
||||
===============================================
|
||||
| 102 | auto/auto |
|
||||
===============================================
|
||||
Presto compilation completed successfully. (ahblite)
|
||||
Information: Building the design 'hazard'. (HDL-193)
|
||||
Presto compilation completed successfully. (hazard)
|
||||
Information: Building the design 'busdp' instantiated from design 'ifu' with
|
||||
the parameters "1,32,1". (HDL-193)
|
||||
Presto compilation completed successfully. (busdp_WORDSPERLINE1_LINELEN32_LOGWPL1)
|
||||
Information: Building the design 'mux2' instantiated from design 'ifu' with
|
||||
the parameters "32". (HDL-193)
|
||||
Presto compilation completed successfully. (mux2_WIDTH32)
|
||||
Information: Building the design 'flopenl' instantiated from design 'ifu' with
|
||||
the parameters "32". (HDL-193)
|
||||
|
||||
Inferred memory devices in process
|
||||
in routine flopenl_WIDTH32 line 40 in file
|
||||
'./hdl/flopenl.sv'.
|
||||
===============================================================================
|
||||
| Register Name | Type | Width | Bus | MB | AR | AS | SR | SS | ST |
|
||||
===============================================================================
|
||||
| q_reg | Flip-flop | 32 | Y | N | N | N | N | N | N |
|
||||
===============================================================================
|
||||
Presto compilation completed successfully. (flopenl_WIDTH32)
|
||||
Information: Building the design 'flopenrc' instantiated from design 'ifu' with
|
||||
the parameters "32". (HDL-193)
|
||||
|
||||
Inferred memory devices in process
|
||||
in routine flopenrc_WIDTH32 line 39 in file
|
||||
'./hdl/flopenrc.sv'.
|
||||
===============================================================================
|
||||
| Register Name | Type | Width | Bus | MB | AR | AS | SR | SS | ST |
|
||||
===============================================================================
|
||||
| q_reg | Flip-flop | 32 | Y | N | N | N | N | N | N |
|
||||
===============================================================================
|
||||
Presto compilation completed successfully. (flopenrc_WIDTH32)
|
||||
Information: Building the design 'decompress'. (HDL-193)
|
||||
Presto compilation completed successfully. (decompress)
|
||||
Information: Building the design 'flopenr' instantiated from design 'ifu' with
|
||||
the parameters "1". (HDL-193)
|
||||
|
||||
Inferred memory devices in process
|
||||
in routine flopenr_WIDTH1 line 39 in file
|
||||
'./hdl/flopenr.sv'.
|
||||
===============================================================================
|
||||
| Register Name | Type | Width | Bus | MB | AR | AS | SR | SS | ST |
|
||||
===============================================================================
|
||||
| q_reg | Flip-flop | 1 | N | N | N | N | N | N | N |
|
||||
===============================================================================
|
||||
Presto compilation completed successfully. (flopenr_WIDTH1)
|
||||
Information: Building the design 'flopenr' instantiated from design 'ifu' with
|
||||
the parameters "32". (HDL-193)
|
||||
|
||||
Inferred memory devices in process
|
||||
in routine flopenr_WIDTH32 line 39 in file
|
||||
'./hdl/flopenr.sv'.
|
||||
===============================================================================
|
||||
| Register Name | Type | Width | Bus | MB | AR | AS | SR | SS | ST |
|
||||
===============================================================================
|
||||
| q_reg | Flip-flop | 32 | Y | N | N | N | N | N | N |
|
||||
===============================================================================
|
||||
Presto compilation completed successfully. (flopenr_WIDTH32)
|
||||
Information: Building the design 'controller'. (HDL-193)
|
||||
Warning: ./hdl/controller.sv:145: Statement unreachable (Branch condition impossible to meet). (VER-61)
|
||||
|
||||
Statistics for case statements in always block at line 118 in file
|
||||
'./hdl/controller.sv'
|
||||
===============================================
|
||||
| Line | full/ parallel |
|
||||
===============================================
|
||||
| 119 | auto/auto |
|
||||
===============================================
|
||||
Presto compilation completed successfully. (controller)
|
||||
Information: Building the design 'datapath'. (HDL-193)
|
||||
Presto compilation completed successfully. (datapath)
|
||||
Information: Building the design 'forward'. (HDL-193)
|
||||
Presto compilation completed successfully. (forward)
|
||||
Information: Building the design 'busdp' instantiated from design 'lsu' with
|
||||
the parameters "1,32,1,1". (HDL-193)
|
||||
Presto compilation completed successfully. (busdp_WORDSPERLINE1_LINELEN32_LOGWPL1_LSU1)
|
||||
Information: Building the design 'subwordread'. (HDL-193)
|
||||
|
||||
Statistics for case statements in always block at line 91 in file
|
||||
'./hdl/subwordread.sv'
|
||||
===============================================
|
||||
| Line | full/ parallel |
|
||||
===============================================
|
||||
| 92 | auto/auto |
|
||||
===============================================
|
||||
|
||||
Statistics for case statements in always block at line 100 in file
|
||||
'./hdl/subwordread.sv'
|
||||
===============================================
|
||||
| Line | full/ parallel |
|
||||
===============================================
|
||||
| 101 | auto/auto |
|
||||
===============================================
|
||||
|
||||
Statistics for case statements in always block at line 107 in file
|
||||
'./hdl/subwordread.sv'
|
||||
===============================================
|
||||
| Line | full/ parallel |
|
||||
===============================================
|
||||
| 108 | auto/auto |
|
||||
===============================================
|
||||
Presto compilation completed successfully. (subwordread)
|
||||
Information: Building the design 'flopenl' instantiated from design 'ahblite' with
|
||||
the parameters "TYPE="enum(24%array(0%1%0%logic)%4%ahblite:_Pr0QaORKb_%cons(4%IDLE%00%cons(4%MEMREAD%01%cons(4%MEMWRITE%10%cons(4%INSTRREAD%11%null)))))%FpfRxH&"". (HDL-193)
|
||||
|
||||
Inferred memory devices in process
|
||||
in routine flopenl_370242 line 40 in file
|
||||
'./hdl/flopenl.sv'.
|
||||
===============================================================================
|
||||
| Register Name | Type | Width | Bus | MB | AR | AS | SR | SS | ST |
|
||||
===============================================================================
|
||||
| q_reg | Flip-flop | 2 | Y | N | N | N | N | N | N |
|
||||
===============================================================================
|
||||
Presto compilation completed successfully. (flopenl_370242)
|
||||
Information: Building the design 'flop' instantiated from design 'ahblite' with
|
||||
the parameters "32". (HDL-193)
|
||||
|
||||
Inferred memory devices in process
|
||||
in routine flop_WIDTH32 line 39 in file
|
||||
'./hdl/flop.sv'.
|
||||
===============================================================================
|
||||
| Register Name | Type | Width | Bus | MB | AR | AS | SR | SS | ST |
|
||||
===============================================================================
|
||||
| q_reg | Flip-flop | 32 | Y | N | N | N | N | N | N |
|
||||
===============================================================================
|
||||
Presto compilation completed successfully. (flop_WIDTH32)
|
||||
Information: Building the design 'flop' instantiated from design 'ahblite' with
|
||||
the parameters "3". (HDL-193)
|
||||
|
||||
Inferred memory devices in process
|
||||
in routine flop_WIDTH3 line 39 in file
|
||||
'./hdl/flop.sv'.
|
||||
===============================================================================
|
||||
| Register Name | Type | Width | Bus | MB | AR | AS | SR | SS | ST |
|
||||
===============================================================================
|
||||
| q_reg | Flip-flop | 3 | Y | N | N | N | N | N | N |
|
||||
===============================================================================
|
||||
Presto compilation completed successfully. (flop_WIDTH3)
|
||||
Information: Building the design 'flop' instantiated from design 'ahblite' with
|
||||
the parameters "4". (HDL-193)
|
||||
|
||||
Inferred memory devices in process
|
||||
in routine flop_WIDTH4 line 39 in file
|
||||
'./hdl/flop.sv'.
|
||||
===============================================================================
|
||||
| Register Name | Type | Width | Bus | MB | AR | AS | SR | SS | ST |
|
||||
===============================================================================
|
||||
| q_reg | Flip-flop | 4 | Y | N | N | N | N | N | N |
|
||||
===============================================================================
|
||||
Presto compilation completed successfully. (flop_WIDTH4)
|
||||
Information: Building the design 'flop' instantiated from design 'ahblite' with
|
||||
the parameters "1". (HDL-193)
|
||||
|
||||
Inferred memory devices in process
|
||||
in routine flop_WIDTH1 line 39 in file
|
||||
'./hdl/flop.sv'.
|
||||
===============================================================================
|
||||
| Register Name | Type | Width | Bus | MB | AR | AS | SR | SS | ST |
|
||||
===============================================================================
|
||||
| q_reg | Flip-flop | 1 | N | N | N | N | N | N | N |
|
||||
===============================================================================
|
||||
Presto compilation completed successfully. (flop_WIDTH1)
|
||||
Information: Building the design 'flopen' instantiated from design 'busdp_WORDSPERLINE1_LINELEN32_LOGWPL1' with
|
||||
the parameters "32". (HDL-193)
|
||||
|
||||
Inferred memory devices in process
|
||||
in routine flopen_WIDTH32 line 39 in file
|
||||
'./hdl/flopen.sv'.
|
||||
===============================================================================
|
||||
| Register Name | Type | Width | Bus | MB | AR | AS | SR | SS | ST |
|
||||
===============================================================================
|
||||
| q_reg | Flip-flop | 32 | Y | N | N | N | N | N | N |
|
||||
===============================================================================
|
||||
Presto compilation completed successfully. (flopen_WIDTH32)
|
||||
Information: Building the design 'mux2' instantiated from design 'busdp_WORDSPERLINE1_LINELEN32_LOGWPL1' with
|
||||
the parameters "34". (HDL-193)
|
||||
Presto compilation completed successfully. (mux2_WIDTH34)
|
||||
Information: Building the design 'mux2' instantiated from design 'busdp_WORDSPERLINE1_LINELEN32_LOGWPL1' with
|
||||
the parameters "3". (HDL-193)
|
||||
Presto compilation completed successfully. (mux2_WIDTH3)
|
||||
Information: Building the design 'busfsm' instantiated from design 'busdp_WORDSPERLINE1_LINELEN32_LOGWPL1' with
|
||||
the parameters "0,1,1'h0". (HDL-193)
|
||||
Warning: ./hdl/busfsm.sv:98: DEFAULT branch of CASE statement cannot be reached. (ELAB-311)
|
||||
|
||||
Statistics for case statements in always block at line 97 in file
|
||||
'./hdl/busfsm.sv'
|
||||
===============================================
|
||||
| Line | full/ parallel |
|
||||
===============================================
|
||||
| 98 | auto/auto |
|
||||
===============================================
|
||||
|
||||
Inferred memory devices in process
|
||||
in routine busfsm_0_1_0 line 93 in file
|
||||
'./hdl/busfsm.sv'.
|
||||
===============================================================================
|
||||
| Register Name | Type | Width | Bus | MB | AR | AS | SR | SS | ST |
|
||||
===============================================================================
|
||||
| BusCurrState_reg | Flip-flop | 3 | Y | N | N | N | N | N | N |
|
||||
===============================================================================
|
||||
Presto compilation completed successfully. (busfsm_0_1_0)
|
||||
Information: Building the design 'flopenrc' instantiated from design 'controller' with
|
||||
the parameters "1". (HDL-193)
|
||||
|
||||
Inferred memory devices in process
|
||||
in routine flopenrc_WIDTH1 line 39 in file
|
||||
'./hdl/flopenrc.sv'.
|
||||
===============================================================================
|
||||
| Register Name | Type | Width | Bus | MB | AR | AS | SR | SS | ST |
|
||||
===============================================================================
|
||||
| q_reg | Flip-flop | 1 | N | N | N | N | N | N | N |
|
||||
===============================================================================
|
||||
Presto compilation completed successfully. (flopenrc_WIDTH1)
|
||||
Information: Building the design 'flopenrc' instantiated from design 'controller' with
|
||||
the parameters "27". (HDL-193)
|
||||
|
||||
Inferred memory devices in process
|
||||
in routine flopenrc_WIDTH27 line 39 in file
|
||||
'./hdl/flopenrc.sv'.
|
||||
===============================================================================
|
||||
| Register Name | Type | Width | Bus | MB | AR | AS | SR | SS | ST |
|
||||
===============================================================================
|
||||
| q_reg | Flip-flop | 27 | Y | N | N | N | N | N | N |
|
||||
===============================================================================
|
||||
Presto compilation completed successfully. (flopenrc_WIDTH27)
|
||||
Information: Building the design 'mux4' instantiated from design 'controller' with
|
||||
the parameters "1". (HDL-193)
|
||||
Presto compilation completed successfully. (mux4_WIDTH1)
|
||||
Information: Building the design 'flopenrc' instantiated from design 'controller' with
|
||||
the parameters "18". (HDL-193)
|
||||
|
||||
Inferred memory devices in process
|
||||
in routine flopenrc_WIDTH18 line 39 in file
|
||||
'./hdl/flopenrc.sv'.
|
||||
===============================================================================
|
||||
| Register Name | Type | Width | Bus | MB | AR | AS | SR | SS | ST |
|
||||
===============================================================================
|
||||
| q_reg | Flip-flop | 18 | Y | N | N | N | N | N | N |
|
||||
===============================================================================
|
||||
Presto compilation completed successfully. (flopenrc_WIDTH18)
|
||||
Information: Building the design 'flopenrc' instantiated from design 'controller' with
|
||||
the parameters "4". (HDL-193)
|
||||
|
||||
Inferred memory devices in process
|
||||
in routine flopenrc_WIDTH4 line 39 in file
|
||||
'./hdl/flopenrc.sv'.
|
||||
===============================================================================
|
||||
| Register Name | Type | Width | Bus | MB | AR | AS | SR | SS | ST |
|
||||
===============================================================================
|
||||
| q_reg | Flip-flop | 4 | Y | N | N | N | N | N | N |
|
||||
===============================================================================
|
||||
Presto compilation completed successfully. (flopenrc_WIDTH4)
|
||||
Information: Building the design 'regfile'. (HDL-193)
|
||||
|
||||
Inferred memory devices in process
|
||||
in routine regfile line 54 in file
|
||||
'./hdl/regfile.sv'.
|
||||
===============================================================================
|
||||
| Register Name | Type | Width | Bus | MB | AR | AS | SR | SS | ST |
|
||||
===============================================================================
|
||||
| rf_reg | Flip-flop | 480 | Y | N | N | N | N | N | N |
|
||||
===============================================================================
|
||||
Statistics for MUX_OPs
|
||||
======================================================
|
||||
| block name/line | Inputs | Outputs | # sel inputs |
|
||||
======================================================
|
||||
| regfile/58 | 16 | 32 | 4 |
|
||||
| regfile/59 | 16 | 32 | 4 |
|
||||
======================================================
|
||||
Presto compilation completed successfully. (regfile)
|
||||
Information: Building the design 'extend'. (HDL-193)
|
||||
|
||||
Statistics for case statements in always block at line 40 in file
|
||||
'./hdl/extend.sv'
|
||||
===============================================
|
||||
| Line | full/ parallel |
|
||||
===============================================
|
||||
| 41 | auto/auto |
|
||||
===============================================
|
||||
Presto compilation completed successfully. (extend)
|
||||
Information: Building the design 'flopenrc' instantiated from design 'datapath' with
|
||||
the parameters "5". (HDL-193)
|
||||
|
||||
Inferred memory devices in process
|
||||
in routine flopenrc_WIDTH5 line 39 in file
|
||||
'./hdl/flopenrc.sv'.
|
||||
===============================================================================
|
||||
| Register Name | Type | Width | Bus | MB | AR | AS | SR | SS | ST |
|
||||
===============================================================================
|
||||
| q_reg | Flip-flop | 5 | Y | N | N | N | N | N | N |
|
||||
===============================================================================
|
||||
Presto compilation completed successfully. (flopenrc_WIDTH5)
|
||||
Information: Building the design 'mux3' instantiated from design 'datapath' with
|
||||
the parameters "32". (HDL-193)
|
||||
Presto compilation completed successfully. (mux3_WIDTH32)
|
||||
Information: Building the design 'comparator' instantiated from design 'datapath' with
|
||||
the parameters "32". (HDL-193)
|
||||
Presto compilation completed successfully. (comparator_WIDTH32)
|
||||
Information: Building the design 'alu' instantiated from design 'datapath' with
|
||||
the parameters "32". (HDL-193)
|
||||
|
||||
Statistics for case statements in always block at line 74 in file
|
||||
'./hdl/alu.sv'
|
||||
===============================================
|
||||
| Line | full/ parallel |
|
||||
===============================================
|
||||
| 75 | auto/auto |
|
||||
===============================================
|
||||
Presto compilation completed successfully. (alu_WIDTH32)
|
||||
Information: Building the design 'mux5' instantiated from design 'datapath' with
|
||||
the parameters "32". (HDL-193)
|
||||
Presto compilation completed successfully. (mux5_WIDTH32)
|
||||
Information: Building the design 'shifter'. (HDL-193)
|
||||
Presto compilation completed successfully. (shifter)
|
||||
1
|
||||
# Set the current_design
|
||||
current_design $my_toplevel
|
||||
Current design is 'wallypipelinedcore'.
|
||||
{wallypipelinedcore}
|
||||
link
|
||||
|
||||
Linking design 'wallypipelinedcore'
|
||||
Using the following designs and libraries:
|
||||
--------------------------------------------------------------------------
|
||||
dw_foundation.sldb (library) /cad/synopsys/SYN/libraries/syn/dw_foundation.sldb
|
||||
|
||||
1
|
||||
# Reset all constraints
|
||||
reset_design
|
||||
1
|
||||
# Power Dissipation Analysis
|
||||
######### OPTIONAL !!!!!!!!!!!!!!!!
|
||||
if { $saifpower == 1 } {
|
||||
read_saif -input power.saif -instance_name testbench/dut/core -auto_map_names -verbose
|
||||
}
|
||||
# Set reset false path
|
||||
set_false_path -from [get_ports reset]
|
||||
1
|
||||
# Set Frequency in [MHz] or period in [ns]
|
||||
set my_clock_pin clk
|
||||
clk
|
||||
set my_uncertainty 0.0
|
||||
0.0
|
||||
set my_clk_freq_MHz $::env(FREQ)
|
||||
500
|
||||
set my_period [expr 1000.0 / $my_clk_freq_MHz]
|
||||
2.0
|
||||
# Create clock object
|
||||
set find_clock [ find port [list $my_clock_pin] ]
|
||||
{clk}
|
||||
if { $find_clock != [list] } {
|
||||
echo "Found clock!"
|
||||
set my_clk $my_clock_pin
|
||||
create_clock -period $my_period $my_clk
|
||||
set_clock_uncertainty $my_uncertainty [get_clocks $my_clk]
|
||||
} else {
|
||||
echo "Did not find clock! Design is probably combinational!"
|
||||
set my_clk vclk
|
||||
create_clock -period $my_period -name $my_clk
|
||||
}
|
||||
Found clock!
|
||||
1
|
||||
# Optimize paths that are close to critical
|
||||
set_critical_range [expr $my_period*0.05] $current_design
|
||||
1
|
||||
# Partitioning - flatten or hierarchically synthesize
|
||||
if { $maxopt == 1 } {
|
||||
ungroup -all -flatten -simple_names
|
||||
}
|
||||
# Set input pins except clock
|
||||
set all_in_ex_clk [remove_from_collection [all_inputs] [get_ports $my_clk]]
|
||||
{reset TimerIntM ExtIntM SwIntM MTIME_CLINT[63] MTIME_CLINT[62] MTIME_CLINT[61] MTIME_CLINT[60] MTIME_CLINT[59] MTIME_CLINT[58] MTIME_CLINT[57] MTIME_CLINT[56] MTIME_CLINT[55] MTIME_CLINT[54] MTIME_CLINT[53] MTIME_CLINT[52] MTIME_CLINT[51] MTIME_CLINT[50] MTIME_CLINT[49] MTIME_CLINT[48] MTIME_CLINT[47] MTIME_CLINT[46] MTIME_CLINT[45] MTIME_CLINT[44] MTIME_CLINT[43] MTIME_CLINT[42] MTIME_CLINT[41] MTIME_CLINT[40] MTIME_CLINT[39] MTIME_CLINT[38] MTIME_CLINT[37] MTIME_CLINT[36] MTIME_CLINT[35] MTIME_CLINT[34] MTIME_CLINT[33] MTIME_CLINT[32] MTIME_CLINT[31] MTIME_CLINT[30] MTIME_CLINT[29] MTIME_CLINT[28] MTIME_CLINT[27] MTIME_CLINT[26] MTIME_CLINT[25] MTIME_CLINT[24] MTIME_CLINT[23] MTIME_CLINT[22] MTIME_CLINT[21] MTIME_CLINT[20] MTIME_CLINT[19] MTIME_CLINT[18] MTIME_CLINT[17] MTIME_CLINT[16] MTIME_CLINT[15] MTIME_CLINT[14] MTIME_CLINT[13] MTIME_CLINT[12] MTIME_CLINT[11] MTIME_CLINT[10] MTIME_CLINT[9] MTIME_CLINT[8] MTIME_CLINT[7] MTIME_CLINT[6] MTIME_CLINT[5] MTIME_CLINT[4] MTIME_CLINT[3] MTIME_CLINT[2] MTIME_CLINT[1] MTIME_CLINT[0] HRDATA[31] HRDATA[30] HRDATA[29] HRDATA[28] HRDATA[27] HRDATA[26] HRDATA[25] HRDATA[24] HRDATA[23] HRDATA[22] HRDATA[21] HRDATA[20] HRDATA[19] HRDATA[18] HRDATA[17] HRDATA[16] HRDATA[15] HRDATA[14] HRDATA[13] HRDATA[12] HRDATA[11] HRDATA[10] HRDATA[9] HRDATA[8] HRDATA[7] HRDATA[6] HRDATA[5] HRDATA[4] HRDATA[3] HRDATA[2] HRDATA[1] HRDATA[0] ...}
|
||||
# Specifies delays be propagated through the clock network
|
||||
# This is getting optimized poorly in the current flow, causing a lot of clock skew
|
||||
# and unrealistic bad timing results.
|
||||
# set_propagated_clock [get_clocks $my_clk]
|
||||
# Setting constraints on input ports
|
||||
if {$tech == "sky130"} {
|
||||
set_driving_cell -lib_cell sky130_osu_sc_12T_ms__dff_1 -pin Q $all_in_ex_clk
|
||||
} elseif {$tech == "sky90"} {
|
||||
set_driving_cell -lib_cell scc9gena_dfxbp_1 -pin Q $all_in_ex_clk
|
||||
}
|
||||
# Set input/output delay
|
||||
set_input_delay 0.1 -max -clock $my_clk $all_in_ex_clk
|
||||
1
|
||||
set_output_delay 0.1 -max -clock $my_clk [all_outputs]
|
||||
1
|
||||
# Setting load constraint on output ports
|
||||
if {$tech == "sky130"} {
|
||||
set_load [expr [load_of sky130_osu_sc_12T_ms_TT_1P8_25C.ccs/sky130_osu_sc_12T_ms__dff_1/D] * 1] [all_outputs]
|
||||
} elseif {$tech == "sky90"} {
|
||||
set_load [expr [load_of scc9gena_tt_1.2v_25C/scc9gena_dfxbp_1/D] * 1] [all_outputs]
|
||||
}
|
||||
# Set the wire load model
|
||||
set_wire_load_mode "top"
|
||||
1
|
||||
# Attempt Area Recovery - if looking for minimal area
|
||||
# set_max_area 2000
|
||||
# Set fanout
|
||||
set_max_fanout 6 $all_in_ex_clk
|
||||
1
|
||||
# Fix hold time violations (DH: this doesn't seem to be working right now)
|
||||
#set_fix_hold [all_clocks]
|
||||
# Deal with constants and buffers to isolate ports
|
||||
set_fix_multiple_port_nets -all -buffer_constants
|
||||
1
|
||||
# setting up the group paths to find out the required timings
|
||||
# group_path -name OUTPUTS -to [all_outputs]
|
||||
# group_path -name INPUTS -from [all_inputs]
|
||||
# group_path -name COMBO -from [all_inputs] -to [all_outputs]
|
||||
# Save Unmapped Design
|
||||
#set filename [format "%s%s%s%s" $outputDir "/unmapped/" $my_toplevel ".ddc"]
|
||||
#write_file -format ddc -hierarchy -o $filename
|
||||
# Compile statements
|
||||
if { $maxopt == 1 } {
|
||||
compile_ultra -retime
|
||||
optimize_registers
|
||||
} else {
|
||||
compile_ultra -no_seq_output_inversion -no_boundary_optimization
|
||||
}
|
||||
Information: Auto ungrouping of the design is disabled because the '-no_boundary_optimization' is used. (OPT-1316)
|
||||
Warning: The value of variable 'compile_preserve_subdesign_interfaces' has been changed to true because '-no_boundary_optimization' is used. (OPT-133)
|
||||
Information: Starting from 2013.12 release, constant propagation is enabled even when boundary optimization is disabled. (OPT-1318)
|
||||
Information: Performing power optimization. (PWR-850)
|
||||
Error: No target library found. (OPT-1312)
|
||||
0
|
||||
# Eliminate need for assign statements (yuck!)
|
||||
set verilogout_no_tri true
|
||||
true
|
||||
set verilogout_equation false
|
||||
false
|
||||
# setting to generate output files
|
||||
set write_v 1 ;# generates structual netlist
|
||||
1
|
||||
set write_sdc 1 ;# generates synopsys design constraint file for p&r
|
||||
1
|
||||
set write_ddc 1 ;# compiler file in ddc format
|
||||
1
|
||||
set write_sdf 1 ;# sdf file for backannotated timing sim
|
||||
1
|
||||
set write_pow 1 ;# genrates estimated power report
|
||||
1
|
||||
set write_rep 1 ;# generates estimated area and timing report
|
||||
1
|
||||
set write_cst 1 ;# generate report of constraints
|
||||
1
|
||||
set write_hier 1 ;# generate hierarchy report
|
||||
1
|
||||
# Report Constraint Violators
|
||||
set filename [format "%s%s%s%s" $outputDir "/reports/" $my_toplevel "_constraint_all_violators.rpt"]
|
||||
runs/wallypipelinedcore_rv32e_sky90 nm_500_MHz_2022-03-22-20-43_2947df5b/reports/wallypipelinedcore_constraint_all_violators.rpt
|
||||
redirect $filename {report_constraint -all_violators}
|
||||
Error: could not open output redirect file "runs/wallypipelinedcore_rv32e_sky90 nm_500_MHz_2022-03-22-20-43_2947df5b/reports/wallypipelinedcore_constraint_all_violators.rpt" (CMD-015)
|
||||
# Check design
|
||||
redirect $outputDir/reports/check_design.rpt { check_design }
|
||||
Error: could not open output redirect file "runs/wallypipelinedcore_rv32e_sky90 nm_500_MHz_2022-03-22-20-43_2947df5b/reports/check_design.rpt" (CMD-015)
|
||||
# Report Final Netlist (Hierarchical)
|
||||
set filename [format "%s%s%s%s" $outputDir "/mapped/" $my_toplevel ".sv"]
|
||||
runs/wallypipelinedcore_rv32e_sky90 nm_500_MHz_2022-03-22-20-43_2947df5b/mapped/wallypipelinedcore.sv
|
||||
write_file -f verilog -hierarchy -output $filename
|
||||
Error: Can't open export file '/home/mmasser-frye/riscv-wally/synthDC/runs/wallypipelinedcore_rv32e_sky90 nm_500_MHz_2022-03-22-20-43_2947df5b/mapped/wallypipelinedcore.sv'. (EXPT-4)
|
||||
Error: Write command failed. (UID-25)
|
||||
0
|
||||
set filename [format "%s%s%s%s" $outputDir "/mapped/" $my_toplevel ".sdc"]
|
||||
runs/wallypipelinedcore_rv32e_sky90 nm_500_MHz_2022-03-22-20-43_2947df5b/mapped/wallypipelinedcore.sdc
|
||||
write_sdc $filename
|
||||
Error: Cannot write the 'runs/wallypipelinedcore_rv32e_sky90 nm_500_MHz_2022-03-22-20-43_2947df5b/mapped/wallypipelinedcore.sdc' script file. (UID-270)
|
||||
0
|
||||
set filename [format "%s%s%s%s" $outputDir "/mapped/" $my_toplevel ".ddc"]
|
||||
runs/wallypipelinedcore_rv32e_sky90 nm_500_MHz_2022-03-22-20-43_2947df5b/mapped/wallypipelinedcore.ddc
|
||||
write_file -format ddc -hierarchy -o $filename
|
||||
Error: Unable to open DDC file 'runs/wallypipelinedcore_rv32e_sky90 nm_500_MHz_2022-03-22-20-43_2947df5b/mapped/wallypipelinedcore.ddc' for writing. (DDC-1)
|
||||
Error: Write command failed. (UID-25)
|
||||
0
|
||||
set filename [format "%s%s%s%s" $outputDir "/mapped/" $my_toplevel ".sdf"]
|
||||
runs/wallypipelinedcore_rv32e_sky90 nm_500_MHz_2022-03-22-20-43_2947df5b/mapped/wallypipelinedcore.sdf
|
||||
write_sdf $filename
|
||||
Information: Annotated 'cell' delays are assumed to include load delay. (UID-282)
|
||||
Error: Cannot write the '/home/mmasser-frye/riscv-wally/synthDC/runs/wallypipelinedcore_rv32e_sky90 nm_500_MHz_2022-03-22-20-43_2947df5b/mapped/wallypipelinedcore.sdf' file. (UID-29)
|
||||
0
|
||||
# QoR
|
||||
set filename [format "%s%s%s%s" $outputDir "/reports/" $my_toplevel "_qor.rep"]
|
||||
runs/wallypipelinedcore_rv32e_sky90 nm_500_MHz_2022-03-22-20-43_2947df5b/reports/wallypipelinedcore_qor.rep
|
||||
redirect $filename { report_qor }
|
||||
Error: could not open output redirect file "runs/wallypipelinedcore_rv32e_sky90 nm_500_MHz_2022-03-22-20-43_2947df5b/reports/wallypipelinedcore_qor.rep" (CMD-015)
|
||||
# Report Timing
|
||||
set filename [format "%s%s%s%s" $outputDir "/reports/" $my_toplevel "_reportpath.rep"]
|
||||
runs/wallypipelinedcore_rv32e_sky90 nm_500_MHz_2022-03-22-20-43_2947df5b/reports/wallypipelinedcore_reportpath.rep
|
||||
#redirect $filename { report_path_group }
|
||||
set filename [format "%s%s%s%s" $outputDir "/reports/" $my_toplevel "_report_clock.rep"]
|
||||
runs/wallypipelinedcore_rv32e_sky90 nm_500_MHz_2022-03-22-20-43_2947df5b/reports/wallypipelinedcore_report_clock.rep
|
||||
# redirect $filename { report_clock }
|
||||
set filename [format "%s%s%s%s" $outputDir "/reports/" $my_toplevel "_timing.rep"]
|
||||
runs/wallypipelinedcore_rv32e_sky90 nm_500_MHz_2022-03-22-20-43_2947df5b/reports/wallypipelinedcore_timing.rep
|
||||
redirect $filename { report_timing -capacitance -transition_time -nets -nworst 1 }
|
||||
Error: could not open output redirect file "runs/wallypipelinedcore_rv32e_sky90 nm_500_MHz_2022-03-22-20-43_2947df5b/reports/wallypipelinedcore_timing.rep" (CMD-015)
|
||||
set filename [format "%s%s%s%s" $outputDir "/reports/" $my_toplevel "_mindelay.rep"]
|
||||
runs/wallypipelinedcore_rv32e_sky90 nm_500_MHz_2022-03-22-20-43_2947df5b/reports/wallypipelinedcore_mindelay.rep
|
||||
redirect $filename { report_timing -capacitance -transition_time -nets -delay_type min -nworst 1 }
|
||||
Error: could not open output redirect file "runs/wallypipelinedcore_rv32e_sky90 nm_500_MHz_2022-03-22-20-43_2947df5b/reports/wallypipelinedcore_mindelay.rep" (CMD-015)
|
||||
set filename [format "%s%s%s%s" $outputDir "/reports/" $my_toplevel "_per_module_timing.rep"]
|
||||
runs/wallypipelinedcore_rv32e_sky90 nm_500_MHz_2022-03-22-20-43_2947df5b/reports/wallypipelinedcore_per_module_timing.rep
|
||||
redirect -append $filename { echo "\n\n\n//// Critical paths through ifu ////\n\n\n" }
|
||||
Error: could not open output redirect file "runs/wallypipelinedcore_rv32e_sky90 nm_500_MHz_2022-03-22-20-43_2947df5b/reports/wallypipelinedcore_per_module_timing.rep" (CMD-015)
|
||||
redirect -append $filename { report_timing -capacitance -transition_time -nets -through {ifu/*} -nworst 1 }
|
||||
Error: could not open output redirect file "runs/wallypipelinedcore_rv32e_sky90 nm_500_MHz_2022-03-22-20-43_2947df5b/reports/wallypipelinedcore_per_module_timing.rep" (CMD-015)
|
||||
redirect -append $filename { echo "\n\n\n//// Critical paths through ieu ////\n\n\n" }
|
||||
Error: could not open output redirect file "runs/wallypipelinedcore_rv32e_sky90 nm_500_MHz_2022-03-22-20-43_2947df5b/reports/wallypipelinedcore_per_module_timing.rep" (CMD-015)
|
||||
redirect -append $filename { report_timing -capacitance -transition_time -nets -through {ieu/*} -nworst 1 }
|
||||
Error: could not open output redirect file "runs/wallypipelinedcore_rv32e_sky90 nm_500_MHz_2022-03-22-20-43_2947df5b/reports/wallypipelinedcore_per_module_timing.rep" (CMD-015)
|
||||
redirect -append $filename { echo "\n\n\n//// Critical paths through lsu ////\n\n\n" }
|
||||
Error: could not open output redirect file "runs/wallypipelinedcore_rv32e_sky90 nm_500_MHz_2022-03-22-20-43_2947df5b/reports/wallypipelinedcore_per_module_timing.rep" (CMD-015)
|
||||
redirect -append $filename { report_timing -capacitance -transition_time -nets -through {lsu/*} -nworst 1 }
|
||||
Error: could not open output redirect file "runs/wallypipelinedcore_rv32e_sky90 nm_500_MHz_2022-03-22-20-43_2947df5b/reports/wallypipelinedcore_per_module_timing.rep" (CMD-015)
|
||||
redirect -append $filename { echo "\n\n\n//// Critical paths through ebu (ahblite) ////\n\n\n" }
|
||||
Error: could not open output redirect file "runs/wallypipelinedcore_rv32e_sky90 nm_500_MHz_2022-03-22-20-43_2947df5b/reports/wallypipelinedcore_per_module_timing.rep" (CMD-015)
|
||||
redirect -append $filename { report_timing -capacitance -transition_time -nets -through {ebu/*} -nworst 1 }
|
||||
Error: could not open output redirect file "runs/wallypipelinedcore_rv32e_sky90 nm_500_MHz_2022-03-22-20-43_2947df5b/reports/wallypipelinedcore_per_module_timing.rep" (CMD-015)
|
||||
redirect -append $filename { echo "\n\n\n//// Critical paths through mdu ////\n\n\n" }
|
||||
Error: could not open output redirect file "runs/wallypipelinedcore_rv32e_sky90 nm_500_MHz_2022-03-22-20-43_2947df5b/reports/wallypipelinedcore_per_module_timing.rep" (CMD-015)
|
||||
redirect -append $filename { report_timing -capacitance -transition_time -nets -through {mdu/*} -nworst 1 }
|
||||
Error: could not open output redirect file "runs/wallypipelinedcore_rv32e_sky90 nm_500_MHz_2022-03-22-20-43_2947df5b/reports/wallypipelinedcore_per_module_timing.rep" (CMD-015)
|
||||
redirect -append $filename { echo "\n\n\n//// Critical paths through hzu ////\n\n\n" }
|
||||
Error: could not open output redirect file "runs/wallypipelinedcore_rv32e_sky90 nm_500_MHz_2022-03-22-20-43_2947df5b/reports/wallypipelinedcore_per_module_timing.rep" (CMD-015)
|
||||
redirect -append $filename { report_timing -capacitance -transition_time -nets -through {hzu/*} -nworst 1 }
|
||||
Error: could not open output redirect file "runs/wallypipelinedcore_rv32e_sky90 nm_500_MHz_2022-03-22-20-43_2947df5b/reports/wallypipelinedcore_per_module_timing.rep" (CMD-015)
|
||||
redirect -append $filename { echo "\n\n\n//// Critical paths through priv ////\n\n\n" }
|
||||
Error: could not open output redirect file "runs/wallypipelinedcore_rv32e_sky90 nm_500_MHz_2022-03-22-20-43_2947df5b/reports/wallypipelinedcore_per_module_timing.rep" (CMD-015)
|
||||
redirect -append $filename { report_timing -capacitance -transition_time -nets -through {priv/*} -nworst 1 }
|
||||
Error: could not open output redirect file "runs/wallypipelinedcore_rv32e_sky90 nm_500_MHz_2022-03-22-20-43_2947df5b/reports/wallypipelinedcore_per_module_timing.rep" (CMD-015)
|
||||
redirect -append $filename { echo "\n\n\n//// Critical paths through fpu ////\n\n\n" }
|
||||
Error: could not open output redirect file "runs/wallypipelinedcore_rv32e_sky90 nm_500_MHz_2022-03-22-20-43_2947df5b/reports/wallypipelinedcore_per_module_timing.rep" (CMD-015)
|
||||
redirect -append $filename { report_timing -capacitance -transition_time -nets -through {fpu/*} -nworst 1 }
|
||||
Error: could not open output redirect file "runs/wallypipelinedcore_rv32e_sky90 nm_500_MHz_2022-03-22-20-43_2947df5b/reports/wallypipelinedcore_per_module_timing.rep" (CMD-015)
|
||||
set filename [format "%s%s%s%s" $outputDir "/reports/" $my_toplevel "_mdu_timing.rep"]
|
||||
runs/wallypipelinedcore_rv32e_sky90 nm_500_MHz_2022-03-22-20-43_2947df5b/reports/wallypipelinedcore_mdu_timing.rep
|
||||
redirect -append $filename { echo "\n\n\n//// Critical paths through entire mdu ////\n\n\n" }
|
||||
Error: could not open output redirect file "runs/wallypipelinedcore_rv32e_sky90 nm_500_MHz_2022-03-22-20-43_2947df5b/reports/wallypipelinedcore_mdu_timing.rep" (CMD-015)
|
||||
redirect -append $filename { report_timing -capacitance -transition_time -nets -through {mdu/*} -nworst 1 }
|
||||
Error: could not open output redirect file "runs/wallypipelinedcore_rv32e_sky90 nm_500_MHz_2022-03-22-20-43_2947df5b/reports/wallypipelinedcore_mdu_timing.rep" (CMD-015)
|
||||
redirect -append $filename { echo "\n\n\n//// Critical paths through multiply unit ////\n\n\n" }
|
||||
Error: could not open output redirect file "runs/wallypipelinedcore_rv32e_sky90 nm_500_MHz_2022-03-22-20-43_2947df5b/reports/wallypipelinedcore_mdu_timing.rep" (CMD-015)
|
||||
redirect -append $filename { report_timing -capacitance -transition_time -nets -through {mdu/genblk1.mul/*} -nworst 1 }
|
||||
Error: could not open output redirect file "runs/wallypipelinedcore_rv32e_sky90 nm_500_MHz_2022-03-22-20-43_2947df5b/reports/wallypipelinedcore_mdu_timing.rep" (CMD-015)
|
||||
redirect -append $filename { echo "\n\n\n//// Critical paths through redundant multiplier ////\n\n\n" }
|
||||
Error: could not open output redirect file "runs/wallypipelinedcore_rv32e_sky90 nm_500_MHz_2022-03-22-20-43_2947df5b/reports/wallypipelinedcore_mdu_timing.rep" (CMD-015)
|
||||
redirect -append $filename { report_timing -capacitance -transition_time -nets -through {mdu/genblk1.mul/bigmul/*} -nworst 1 }
|
||||
Error: could not open output redirect file "runs/wallypipelinedcore_rv32e_sky90 nm_500_MHz_2022-03-22-20-43_2947df5b/reports/wallypipelinedcore_mdu_timing.rep" (CMD-015)
|
||||
redirect -append $filename { echo "\n\n\n//// Critical path through ProdM (mul output) ////\n\n\n" }
|
||||
Error: could not open output redirect file "runs/wallypipelinedcore_rv32e_sky90 nm_500_MHz_2022-03-22-20-43_2947df5b/reports/wallypipelinedcore_mdu_timing.rep" (CMD-015)
|
||||
redirect -append $filename { report_timing -capacitance -transition_time -nets -through {mdu/genblk1.ProdM} -nworst 1 }
|
||||
Error: could not open output redirect file "runs/wallypipelinedcore_rv32e_sky90 nm_500_MHz_2022-03-22-20-43_2947df5b/reports/wallypipelinedcore_mdu_timing.rep" (CMD-015)
|
||||
redirect -append $filename { echo "\n\n\n//// Critical path through PP0E (mul partial product) ////\n\n\n" }
|
||||
Error: could not open output redirect file "runs/wallypipelinedcore_rv32e_sky90 nm_500_MHz_2022-03-22-20-43_2947df5b/reports/wallypipelinedcore_mdu_timing.rep" (CMD-015)
|
||||
redirect -append $filename { report_timing -capacitance -transition_time -nets -through {mdu/genblk1.mul/PP0E} -nworst 1 }
|
||||
Error: could not open output redirect file "runs/wallypipelinedcore_rv32e_sky90 nm_500_MHz_2022-03-22-20-43_2947df5b/reports/wallypipelinedcore_mdu_timing.rep" (CMD-015)
|
||||
redirect -append $filename { echo "\n\n\n//// Critical paths through divide unit ////\n\n\n" }
|
||||
Error: could not open output redirect file "runs/wallypipelinedcore_rv32e_sky90 nm_500_MHz_2022-03-22-20-43_2947df5b/reports/wallypipelinedcore_mdu_timing.rep" (CMD-015)
|
||||
redirect -append $filename { report_timing -capacitance -transition_time -nets -through {mdu/genblk1.div/*} -nworst 1 }
|
||||
Error: could not open output redirect file "runs/wallypipelinedcore_rv32e_sky90 nm_500_MHz_2022-03-22-20-43_2947df5b/reports/wallypipelinedcore_mdu_timing.rep" (CMD-015)
|
||||
redirect -append $filename { echo "\n\n\n//// Critical path through QuotM (div output) ////\n\n\n" }
|
||||
Error: could not open output redirect file "runs/wallypipelinedcore_rv32e_sky90 nm_500_MHz_2022-03-22-20-43_2947df5b/reports/wallypipelinedcore_mdu_timing.rep" (CMD-015)
|
||||
redirect -append $filename { report_timing -capacitance -transition_time -nets -through {mdu/genblk1.QuotM} -nworst 1 }
|
||||
Error: could not open output redirect file "runs/wallypipelinedcore_rv32e_sky90 nm_500_MHz_2022-03-22-20-43_2947df5b/reports/wallypipelinedcore_mdu_timing.rep" (CMD-015)
|
||||
redirect -append $filename { echo "\n\n\n//// Critical path through RemM (div output) ////\n\n\n" }
|
||||
Error: could not open output redirect file "runs/wallypipelinedcore_rv32e_sky90 nm_500_MHz_2022-03-22-20-43_2947df5b/reports/wallypipelinedcore_mdu_timing.rep" (CMD-015)
|
||||
redirect -append $filename { report_timing -capacitance -transition_time -nets -through {mdu/genblk1.RemM} -nworst 1 }
|
||||
Error: could not open output redirect file "runs/wallypipelinedcore_rv32e_sky90 nm_500_MHz_2022-03-22-20-43_2947df5b/reports/wallypipelinedcore_mdu_timing.rep" (CMD-015)
|
||||
redirect -append $filename { echo "\n\n\n//// Critical path through div/WNextE ////\n\n\n" }
|
||||
Error: could not open output redirect file "runs/wallypipelinedcore_rv32e_sky90 nm_500_MHz_2022-03-22-20-43_2947df5b/reports/wallypipelinedcore_mdu_timing.rep" (CMD-015)
|
||||
redirect -append $filename { report_timing -capacitance -transition_time -nets -through {mdu/genblk1.div/WNextE} -nworst 1 }
|
||||
Error: could not open output redirect file "runs/wallypipelinedcore_rv32e_sky90 nm_500_MHz_2022-03-22-20-43_2947df5b/reports/wallypipelinedcore_mdu_timing.rep" (CMD-015)
|
||||
redirect -append $filename { echo "\n\n\n//// Critical path through div/XQNextE ////\n\n\n" }
|
||||
Error: could not open output redirect file "runs/wallypipelinedcore_rv32e_sky90 nm_500_MHz_2022-03-22-20-43_2947df5b/reports/wallypipelinedcore_mdu_timing.rep" (CMD-015)
|
||||
redirect -append $filename { report_timing -capacitance -transition_time -nets -through {mdu/genblk1.div/XQNextE} -nworst 1 }
|
||||
Error: could not open output redirect file "runs/wallypipelinedcore_rv32e_sky90 nm_500_MHz_2022-03-22-20-43_2947df5b/reports/wallypipelinedcore_mdu_timing.rep" (CMD-015)
|
||||
redirect -append $filename { echo "\n\n\n//// Critical path through div/DAbsBE ////\n\n\n" }
|
||||
Error: could not open output redirect file "runs/wallypipelinedcore_rv32e_sky90 nm_500_MHz_2022-03-22-20-43_2947df5b/reports/wallypipelinedcore_mdu_timing.rep" (CMD-015)
|
||||
redirect -append $filename { report_timing -capacitance -transition_time -nets -through {mdu/genblk1.div/DAbsBE} -nworst 1 }
|
||||
Error: could not open output redirect file "runs/wallypipelinedcore_rv32e_sky90 nm_500_MHz_2022-03-22-20-43_2947df5b/reports/wallypipelinedcore_mdu_timing.rep" (CMD-015)
|
||||
# set filename [format "%s%s%s%s" $outputDir "/reports/" $my_toplevel "_fpu_timing.rep"]
|
||||
# redirect $filename { echo "\n\n\n//// Critical paths through fma ////\n\n\n" }
|
||||
# redirect -append $filename { report_timing -capacitance -transition_time -nets -through {fpu/fpu.fma/*} -nworst 1 }
|
||||
# redirect -append $filename { echo "\n\n\n//// Critical paths through fpdiv ////\n\n\n" }
|
||||
# redirect -append $filename { report_timing -capacitance -transition_time -nets -through {fpu/fpu.fdivsqrt/*} -nworst 1 }
|
||||
# redirect -append $filename { echo "\n\n\n//// Critical paths through faddcvt ////\n\n\n" }
|
||||
# redirect -append $filename { report_timing -capacitance -transition_time -nets -through {fpu/fpu.faddcvt/*} -nworst 1 }
|
||||
set filename [format "%s%s%s%s" $outputDir "/reports/" $my_toplevel "_ifu_timing.rep"]
|
||||
runs/wallypipelinedcore_rv32e_sky90 nm_500_MHz_2022-03-22-20-43_2947df5b/reports/wallypipelinedcore_ifu_timing.rep
|
||||
redirect -append $filename { echo "\n\n\n//// Critical path through PCF ////\n\n\n" }
|
||||
Error: could not open output redirect file "runs/wallypipelinedcore_rv32e_sky90 nm_500_MHz_2022-03-22-20-43_2947df5b/reports/wallypipelinedcore_ifu_timing.rep" (CMD-015)
|
||||
redirect -append $filename { report_timing -capacitance -transition_time -nets -through {ifu/PCF} -nworst 1 }
|
||||
Error: could not open output redirect file "runs/wallypipelinedcore_rv32e_sky90 nm_500_MHz_2022-03-22-20-43_2947df5b/reports/wallypipelinedcore_ifu_timing.rep" (CMD-015)
|
||||
redirect -append $filename { echo "\n\n\n//// Critical path through PCNextF ////\n\n\n" }
|
||||
Error: could not open output redirect file "runs/wallypipelinedcore_rv32e_sky90 nm_500_MHz_2022-03-22-20-43_2947df5b/reports/wallypipelinedcore_ifu_timing.rep" (CMD-015)
|
||||
redirect -append $filename { report_timing -capacitance -transition_time -nets -through {ifu/PCNextF} -nworst 1 }
|
||||
Error: could not open output redirect file "runs/wallypipelinedcore_rv32e_sky90 nm_500_MHz_2022-03-22-20-43_2947df5b/reports/wallypipelinedcore_ifu_timing.rep" (CMD-015)
|
||||
redirect -append $filename { echo "\n\n\n//// Critical path through FinalInstrRawF ////\n\n\n" }
|
||||
Error: could not open output redirect file "runs/wallypipelinedcore_rv32e_sky90 nm_500_MHz_2022-03-22-20-43_2947df5b/reports/wallypipelinedcore_ifu_timing.rep" (CMD-015)
|
||||
redirect -append $filename { report_timing -capacitance -transition_time -nets -through {ifu/FinalInstrRawF} -nworst 1 }
|
||||
Error: could not open output redirect file "runs/wallypipelinedcore_rv32e_sky90 nm_500_MHz_2022-03-22-20-43_2947df5b/reports/wallypipelinedcore_ifu_timing.rep" (CMD-015)
|
||||
redirect -append $filename { echo "\n\n\n//// Critical path through InstrD ////\n\n\n" }
|
||||
Error: could not open output redirect file "runs/wallypipelinedcore_rv32e_sky90 nm_500_MHz_2022-03-22-20-43_2947df5b/reports/wallypipelinedcore_ifu_timing.rep" (CMD-015)
|
||||
redirect -append $filename { report_timing -capacitance -transition_time -nets -through {ifu/decomp/InstrD} -nworst 1 }
|
||||
Error: could not open output redirect file "runs/wallypipelinedcore_rv32e_sky90 nm_500_MHz_2022-03-22-20-43_2947df5b/reports/wallypipelinedcore_ifu_timing.rep" (CMD-015)
|
||||
set filename [format "%s%s%s%s" $outputDir "/reports/" $my_toplevel "_stall_flush_timing.rep"]
|
||||
runs/wallypipelinedcore_rv32e_sky90 nm_500_MHz_2022-03-22-20-43_2947df5b/reports/wallypipelinedcore_stall_flush_timing.rep
|
||||
redirect -append $filename { echo "\n\n\n//// Critical path through StallD ////\n\n\n" }
|
||||
Error: could not open output redirect file "runs/wallypipelinedcore_rv32e_sky90 nm_500_MHz_2022-03-22-20-43_2947df5b/reports/wallypipelinedcore_stall_flush_timing.rep" (CMD-015)
|
||||
redirect -append $filename { report_timing -capacitance -transition_time -nets -through {ieu/StallD} -nworst 1 }
|
||||
Error: could not open output redirect file "runs/wallypipelinedcore_rv32e_sky90 nm_500_MHz_2022-03-22-20-43_2947df5b/reports/wallypipelinedcore_stall_flush_timing.rep" (CMD-015)
|
||||
redirect -append $filename { echo "\n\n\n//// Critical path through StallE ////\n\n\n" }
|
||||
Error: could not open output redirect file "runs/wallypipelinedcore_rv32e_sky90 nm_500_MHz_2022-03-22-20-43_2947df5b/reports/wallypipelinedcore_stall_flush_timing.rep" (CMD-015)
|
||||
redirect -append $filename { report_timing -capacitance -transition_time -nets -through {ieu/StallE} -nworst 1 }
|
||||
Error: could not open output redirect file "runs/wallypipelinedcore_rv32e_sky90 nm_500_MHz_2022-03-22-20-43_2947df5b/reports/wallypipelinedcore_stall_flush_timing.rep" (CMD-015)
|
||||
redirect -append $filename { echo "\n\n\n//// Critical path through StallM ////\n\n\n" }
|
||||
Error: could not open output redirect file "runs/wallypipelinedcore_rv32e_sky90 nm_500_MHz_2022-03-22-20-43_2947df5b/reports/wallypipelinedcore_stall_flush_timing.rep" (CMD-015)
|
||||
redirect -append $filename { report_timing -capacitance -transition_time -nets -through {ieu/StallM} -nworst 1 }
|
||||
Error: could not open output redirect file "runs/wallypipelinedcore_rv32e_sky90 nm_500_MHz_2022-03-22-20-43_2947df5b/reports/wallypipelinedcore_stall_flush_timing.rep" (CMD-015)
|
||||
redirect -append $filename { echo "\n\n\n//// Critical path through StallW ////\n\n\n" }
|
||||
Error: could not open output redirect file "runs/wallypipelinedcore_rv32e_sky90 nm_500_MHz_2022-03-22-20-43_2947df5b/reports/wallypipelinedcore_stall_flush_timing.rep" (CMD-015)
|
||||
redirect -append $filename { report_timing -capacitance -transition_time -nets -through {ieu/StallW} -nworst 1 }
|
||||
Error: could not open output redirect file "runs/wallypipelinedcore_rv32e_sky90 nm_500_MHz_2022-03-22-20-43_2947df5b/reports/wallypipelinedcore_stall_flush_timing.rep" (CMD-015)
|
||||
redirect -append $filename { echo "\n\n\n//// Critical path through FlushD ////\n\n\n" }
|
||||
Error: could not open output redirect file "runs/wallypipelinedcore_rv32e_sky90 nm_500_MHz_2022-03-22-20-43_2947df5b/reports/wallypipelinedcore_stall_flush_timing.rep" (CMD-015)
|
||||
redirect -append $filename { report_timing -capacitance -transition_time -nets -through {ieu/FlushD} -nworst 1 }
|
||||
Error: could not open output redirect file "runs/wallypipelinedcore_rv32e_sky90 nm_500_MHz_2022-03-22-20-43_2947df5b/reports/wallypipelinedcore_stall_flush_timing.rep" (CMD-015)
|
||||
redirect -append $filename { echo "\n\n\n//// Critical path through FlushE ////\n\n\n" }
|
||||
Error: could not open output redirect file "runs/wallypipelinedcore_rv32e_sky90 nm_500_MHz_2022-03-22-20-43_2947df5b/reports/wallypipelinedcore_stall_flush_timing.rep" (CMD-015)
|
||||
redirect -append $filename { report_timing -capacitance -transition_time -nets -through {ieu/FlushE} -nworst 1 }
|
||||
Error: could not open output redirect file "runs/wallypipelinedcore_rv32e_sky90 nm_500_MHz_2022-03-22-20-43_2947df5b/reports/wallypipelinedcore_stall_flush_timing.rep" (CMD-015)
|
||||
redirect -append $filename { echo "\n\n\n//// Critical path through FlushM ////\n\n\n" }
|
||||
Error: could not open output redirect file "runs/wallypipelinedcore_rv32e_sky90 nm_500_MHz_2022-03-22-20-43_2947df5b/reports/wallypipelinedcore_stall_flush_timing.rep" (CMD-015)
|
||||
redirect -append $filename { report_timing -capacitance -transition_time -nets -through {ieu/FlushM} -nworst 1 }
|
||||
Error: could not open output redirect file "runs/wallypipelinedcore_rv32e_sky90 nm_500_MHz_2022-03-22-20-43_2947df5b/reports/wallypipelinedcore_stall_flush_timing.rep" (CMD-015)
|
||||
redirect -append $filename { echo "\n\n\n//// Critical path through FlushW ////\n\n\n" }
|
||||
Error: could not open output redirect file "runs/wallypipelinedcore_rv32e_sky90 nm_500_MHz_2022-03-22-20-43_2947df5b/reports/wallypipelinedcore_stall_flush_timing.rep" (CMD-015)
|
||||
redirect -append $filename { report_timing -capacitance -transition_time -nets -through {ieu/FlushW} -nworst 1 }
|
||||
Error: could not open output redirect file "runs/wallypipelinedcore_rv32e_sky90 nm_500_MHz_2022-03-22-20-43_2947df5b/reports/wallypipelinedcore_stall_flush_timing.rep" (CMD-015)
|
||||
set filename [format "%s%s%s%s" $outputDir "/reports/" $my_toplevel "_ieu_timing.rep"]
|
||||
runs/wallypipelinedcore_rv32e_sky90 nm_500_MHz_2022-03-22-20-43_2947df5b/reports/wallypipelinedcore_ieu_timing.rep
|
||||
redirect -append $filename { echo "\n\n\n//// Critical path through datapath/R1D ////\n\n\n" }
|
||||
Error: could not open output redirect file "runs/wallypipelinedcore_rv32e_sky90 nm_500_MHz_2022-03-22-20-43_2947df5b/reports/wallypipelinedcore_ieu_timing.rep" (CMD-015)
|
||||
redirect -append $filename { report_timing -capacitance -transition_time -nets -through {ieu/dp/R1D} -nworst 1 }
|
||||
Error: could not open output redirect file "runs/wallypipelinedcore_rv32e_sky90 nm_500_MHz_2022-03-22-20-43_2947df5b/reports/wallypipelinedcore_ieu_timing.rep" (CMD-015)
|
||||
redirect -append $filename { echo "\n\n\n//// Critical path through datapath/R2D ////\n\n\n" }
|
||||
Error: could not open output redirect file "runs/wallypipelinedcore_rv32e_sky90 nm_500_MHz_2022-03-22-20-43_2947df5b/reports/wallypipelinedcore_ieu_timing.rep" (CMD-015)
|
||||
redirect -append $filename { report_timing -capacitance -transition_time -nets -through {ieu/dp/R2D} -nworst 1 }
|
||||
Error: could not open output redirect file "runs/wallypipelinedcore_rv32e_sky90 nm_500_MHz_2022-03-22-20-43_2947df5b/reports/wallypipelinedcore_ieu_timing.rep" (CMD-015)
|
||||
redirect -append $filename { echo "\n\n\n//// Critical path through datapath/SrcAE ////\n\n\n" }
|
||||
Error: could not open output redirect file "runs/wallypipelinedcore_rv32e_sky90 nm_500_MHz_2022-03-22-20-43_2947df5b/reports/wallypipelinedcore_ieu_timing.rep" (CMD-015)
|
||||
redirect -append $filename { report_timing -capacitance -transition_time -nets -through {ieu/dp/SrcAE} -nworst 1 }
|
||||
Error: could not open output redirect file "runs/wallypipelinedcore_rv32e_sky90 nm_500_MHz_2022-03-22-20-43_2947df5b/reports/wallypipelinedcore_ieu_timing.rep" (CMD-015)
|
||||
redirect -append $filename { echo "\n\n\n//// Critical path through datapath/ALUResultE ////\n\n\n" }
|
||||
Error: could not open output redirect file "runs/wallypipelinedcore_rv32e_sky90 nm_500_MHz_2022-03-22-20-43_2947df5b/reports/wallypipelinedcore_ieu_timing.rep" (CMD-015)
|
||||
redirect -append $filename { report_timing -capacitance -transition_time -nets -through {ieu/dp/ALUResultE} -nworst 1 }
|
||||
Error: could not open output redirect file "runs/wallypipelinedcore_rv32e_sky90 nm_500_MHz_2022-03-22-20-43_2947df5b/reports/wallypipelinedcore_ieu_timing.rep" (CMD-015)
|
||||
redirect -append $filename { echo "\n\n\n//// Critical path through datapath/WriteDataW ////\n\n\n" }
|
||||
Error: could not open output redirect file "runs/wallypipelinedcore_rv32e_sky90 nm_500_MHz_2022-03-22-20-43_2947df5b/reports/wallypipelinedcore_ieu_timing.rep" (CMD-015)
|
||||
redirect -append $filename { report_timing -capacitance -transition_time -nets -through {ieu/dp/WriteDataW} -nworst 1 }
|
||||
Error: could not open output redirect file "runs/wallypipelinedcore_rv32e_sky90 nm_500_MHz_2022-03-22-20-43_2947df5b/reports/wallypipelinedcore_ieu_timing.rep" (CMD-015)
|
||||
redirect -append $filename { echo "\n\n\n//// Critical path through datapath/ReadDataM ////\n\n\n" }
|
||||
Error: could not open output redirect file "runs/wallypipelinedcore_rv32e_sky90 nm_500_MHz_2022-03-22-20-43_2947df5b/reports/wallypipelinedcore_ieu_timing.rep" (CMD-015)
|
||||
redirect -append $filename { report_timing -capacitance -transition_time -nets -through {ieu/dp/ReadDataM} -nworst 1 }
|
||||
Error: could not open output redirect file "runs/wallypipelinedcore_rv32e_sky90 nm_500_MHz_2022-03-22-20-43_2947df5b/reports/wallypipelinedcore_ieu_timing.rep" (CMD-015)
|
||||
set filename [format "%s%s%s%s" $outputDir "/reports/" $my_toplevel "_fpu_timing.rep"]
|
||||
runs/wallypipelinedcore_rv32e_sky90 nm_500_MHz_2022-03-22-20-43_2947df5b/reports/wallypipelinedcore_fpu_timing.rep
|
||||
redirect -append $filename { echo "\n\n\n//// Critical paths through fma ////\n\n\n" }
|
||||
Error: could not open output redirect file "runs/wallypipelinedcore_rv32e_sky90 nm_500_MHz_2022-03-22-20-43_2947df5b/reports/wallypipelinedcore_fpu_timing.rep" (CMD-015)
|
||||
redirect -append $filename { report_timing -capacitance -transition_time -nets -through {fpu/fpu.fma/*} -nworst 1 }
|
||||
Error: could not open output redirect file "runs/wallypipelinedcore_rv32e_sky90 nm_500_MHz_2022-03-22-20-43_2947df5b/reports/wallypipelinedcore_fpu_timing.rep" (CMD-015)
|
||||
redirect -append $filename { echo "\n\n\n//// Critical paths through fpdiv ////\n\n\n" }
|
||||
Error: could not open output redirect file "runs/wallypipelinedcore_rv32e_sky90 nm_500_MHz_2022-03-22-20-43_2947df5b/reports/wallypipelinedcore_fpu_timing.rep" (CMD-015)
|
||||
redirect -append $filename { report_timing -capacitance -transition_time -nets -through {fpu/fpu.fdivsqrt/*} -nworst 1 }
|
||||
Error: could not open output redirect file "runs/wallypipelinedcore_rv32e_sky90 nm_500_MHz_2022-03-22-20-43_2947df5b/reports/wallypipelinedcore_fpu_timing.rep" (CMD-015)
|
||||
redirect -append $filename { echo "\n\n\n//// Critical paths through faddcvt ////\n\n\n" }
|
||||
Error: could not open output redirect file "runs/wallypipelinedcore_rv32e_sky90 nm_500_MHz_2022-03-22-20-43_2947df5b/reports/wallypipelinedcore_fpu_timing.rep" (CMD-015)
|
||||
redirect -append $filename { report_timing -capacitance -transition_time -nets -through {fpu/fpu.faddcvt/*} -nworst 1 }
|
||||
Error: could not open output redirect file "runs/wallypipelinedcore_rv32e_sky90 nm_500_MHz_2022-03-22-20-43_2947df5b/reports/wallypipelinedcore_fpu_timing.rep" (CMD-015)
|
||||
redirect -append $filename { echo "\n\n\n//// Critical paths through FMAResM ////\n\n\n" }
|
||||
Error: could not open output redirect file "runs/wallypipelinedcore_rv32e_sky90 nm_500_MHz_2022-03-22-20-43_2947df5b/reports/wallypipelinedcore_fpu_timing.rep" (CMD-015)
|
||||
redirect -append $filename { report_timing -capacitance -transition_time -nets -through {fpu/fpu.FMAResM} -nworst 1 }
|
||||
Error: could not open output redirect file "runs/wallypipelinedcore_rv32e_sky90 nm_500_MHz_2022-03-22-20-43_2947df5b/reports/wallypipelinedcore_fpu_timing.rep" (CMD-015)
|
||||
redirect -append $filename { echo "\n\n\n//// Critical paths through FDivResM ////\n\n\n" }
|
||||
Error: could not open output redirect file "runs/wallypipelinedcore_rv32e_sky90 nm_500_MHz_2022-03-22-20-43_2947df5b/reports/wallypipelinedcore_fpu_timing.rep" (CMD-015)
|
||||
redirect -append $filename { report_timing -capacitance -transition_time -nets -through {fpu/fpu.FDivResM} -nworst 1 }
|
||||
Error: could not open output redirect file "runs/wallypipelinedcore_rv32e_sky90 nm_500_MHz_2022-03-22-20-43_2947df5b/reports/wallypipelinedcore_fpu_timing.rep" (CMD-015)
|
||||
redirect -append $filename { echo "\n\n\n//// Critical paths through FResE ////\n\n\n" }
|
||||
Error: could not open output redirect file "runs/wallypipelinedcore_rv32e_sky90 nm_500_MHz_2022-03-22-20-43_2947df5b/reports/wallypipelinedcore_fpu_timing.rep" (CMD-015)
|
||||
redirect -append $filename { report_timing -capacitance -transition_time -nets -through {fpu/fpu.FResE} -nworst 1 }
|
||||
Error: could not open output redirect file "runs/wallypipelinedcore_rv32e_sky90 nm_500_MHz_2022-03-22-20-43_2947df5b/reports/wallypipelinedcore_fpu_timing.rep" (CMD-015)
|
||||
redirect -append $filename { echo "\n\n\n//// Critical paths through fma/SumE ////\n\n\n" }
|
||||
Error: could not open output redirect file "runs/wallypipelinedcore_rv32e_sky90 nm_500_MHz_2022-03-22-20-43_2947df5b/reports/wallypipelinedcore_fpu_timing.rep" (CMD-015)
|
||||
redirect -append $filename { report_timing -capacitance -transition_time -nets -through {fpu/fpu.fma/SumE} -nworst 1 }
|
||||
Error: could not open output redirect file "runs/wallypipelinedcore_rv32e_sky90 nm_500_MHz_2022-03-22-20-43_2947df5b/reports/wallypipelinedcore_fpu_timing.rep" (CMD-015)
|
||||
redirect -append $filename { echo "\n\n\n//// Critical paths through fma/ProdExpE ////\n\n\n" }
|
||||
Error: could not open output redirect file "runs/wallypipelinedcore_rv32e_sky90 nm_500_MHz_2022-03-22-20-43_2947df5b/reports/wallypipelinedcore_fpu_timing.rep" (CMD-015)
|
||||
redirect -append $filename { report_timing -capacitance -transition_time -nets -through {fpu/fpu.fma/ProdExpE} -nworst 1 }
|
||||
Error: could not open output redirect file "runs/wallypipelinedcore_rv32e_sky90 nm_500_MHz_2022-03-22-20-43_2947df5b/reports/wallypipelinedcore_fpu_timing.rep" (CMD-015)
|
||||
set filename [format "%s%s%s%s" $outputDir "/reports/" $my_toplevel "_mmu_timing.rep"]
|
||||
runs/wallypipelinedcore_rv32e_sky90 nm_500_MHz_2022-03-22-20-43_2947df5b/reports/wallypipelinedcore_mmu_timing.rep
|
||||
redirect -append $filename { echo "\n\n\n//// Critical paths through immu/physicaladdress ////\n\n\n" }
|
||||
Error: could not open output redirect file "runs/wallypipelinedcore_rv32e_sky90 nm_500_MHz_2022-03-22-20-43_2947df5b/reports/wallypipelinedcore_mmu_timing.rep" (CMD-015)
|
||||
redirect -append $filename { report_timing -capacitance -transition_time -nets -through {ifu/immu/PhysicalAddress} -nworst 1 }
|
||||
Error: could not open output redirect file "runs/wallypipelinedcore_rv32e_sky90 nm_500_MHz_2022-03-22-20-43_2947df5b/reports/wallypipelinedcore_mmu_timing.rep" (CMD-015)
|
||||
redirect -append $filename { echo "\n\n\n//// Critical paths through dmmu/physicaladdress ////\n\n\n" }
|
||||
Error: could not open output redirect file "runs/wallypipelinedcore_rv32e_sky90 nm_500_MHz_2022-03-22-20-43_2947df5b/reports/wallypipelinedcore_mmu_timing.rep" (CMD-015)
|
||||
redirect -append $filename { report_timing -capacitance -transition_time -nets -through {lsu/dmmu/PhysicalAddress} -nworst 1 }
|
||||
Error: could not open output redirect file "runs/wallypipelinedcore_rv32e_sky90 nm_500_MHz_2022-03-22-20-43_2947df5b/reports/wallypipelinedcore_mmu_timing.rep" (CMD-015)
|
||||
set filename [format "%s%s%s%s" $outputDir "/reports/" $my_toplevel "_priv_timing.rep"]
|
||||
runs/wallypipelinedcore_rv32e_sky90 nm_500_MHz_2022-03-22-20-43_2947df5b/reports/wallypipelinedcore_priv_timing.rep
|
||||
redirect -append $filename { echo "\n\n\n//// Critical paths through priv/TrapM ////\n\n\n" }
|
||||
Error: could not open output redirect file "runs/wallypipelinedcore_rv32e_sky90 nm_500_MHz_2022-03-22-20-43_2947df5b/reports/wallypipelinedcore_priv_timing.rep" (CMD-015)
|
||||
redirect -append $filename { report_timing -capacitance -transition_time -nets -through {priv/TrapM} -nworst 1 }
|
||||
Error: could not open output redirect file "runs/wallypipelinedcore_rv32e_sky90 nm_500_MHz_2022-03-22-20-43_2947df5b/reports/wallypipelinedcore_priv_timing.rep" (CMD-015)
|
||||
redirect -append $filename { echo "\n\n\n//// Critical paths through priv/CSRReadValM ////\n\n\n" }
|
||||
Error: could not open output redirect file "runs/wallypipelinedcore_rv32e_sky90 nm_500_MHz_2022-03-22-20-43_2947df5b/reports/wallypipelinedcore_priv_timing.rep" (CMD-015)
|
||||
redirect -append $filename { report_timing -capacitance -transition_time -nets -through {priv/csr/CSRReadValM} -nworst 1 }
|
||||
Error: could not open output redirect file "runs/wallypipelinedcore_rv32e_sky90 nm_500_MHz_2022-03-22-20-43_2947df5b/reports/wallypipelinedcore_priv_timing.rep" (CMD-015)
|
||||
redirect -append $filename { echo "\n\n\n//// Critical paths through priv/CSRReadValW ////\n\n\n" }
|
||||
Error: could not open output redirect file "runs/wallypipelinedcore_rv32e_sky90 nm_500_MHz_2022-03-22-20-43_2947df5b/reports/wallypipelinedcore_priv_timing.rep" (CMD-015)
|
||||
redirect -append $filename { report_timing -capacitance -transition_time -nets -through {priv/CSRReadValW} -nworst 1 }
|
||||
Error: could not open output redirect file "runs/wallypipelinedcore_rv32e_sky90 nm_500_MHz_2022-03-22-20-43_2947df5b/reports/wallypipelinedcore_priv_timing.rep" (CMD-015)
|
||||
set filename [format "%s%s%s%s" $outputDir "/reports/" $my_toplevel "_min_timing.rep"]
|
||||
runs/wallypipelinedcore_rv32e_sky90 nm_500_MHz_2022-03-22-20-43_2947df5b/reports/wallypipelinedcore_min_timing.rep
|
||||
redirect $filename { report_timing -delay min }
|
||||
Error: could not open output redirect file "runs/wallypipelinedcore_rv32e_sky90 nm_500_MHz_2022-03-22-20-43_2947df5b/reports/wallypipelinedcore_min_timing.rep" (CMD-015)
|
||||
set filename [format "%s%s%s%s" $outputDir "/reports/" $my_toplevel "_area.rep"]
|
||||
runs/wallypipelinedcore_rv32e_sky90 nm_500_MHz_2022-03-22-20-43_2947df5b/reports/wallypipelinedcore_area.rep
|
||||
redirect $filename { report_area -hierarchy -nosplit -physical -designware}
|
||||
Error: could not open output redirect file "runs/wallypipelinedcore_rv32e_sky90 nm_500_MHz_2022-03-22-20-43_2947df5b/reports/wallypipelinedcore_area.rep" (CMD-015)
|
||||
set filename [format "%s%s%s%s" $outputDir "/reports/" $my_toplevel "_cell.rep"]
|
||||
runs/wallypipelinedcore_rv32e_sky90 nm_500_MHz_2022-03-22-20-43_2947df5b/reports/wallypipelinedcore_cell.rep
|
||||
# redirect $filename { report_cell [get_cells -hier *] }
|
||||
set filename [format "%s%s%s%s" $outputDir "/reports/" $my_toplevel "_power.rep"]
|
||||
runs/wallypipelinedcore_rv32e_sky90 nm_500_MHz_2022-03-22-20-43_2947df5b/reports/wallypipelinedcore_power.rep
|
||||
redirect $filename { report_power -hierarchy -levels 1 }
|
||||
Error: could not open output redirect file "runs/wallypipelinedcore_rv32e_sky90 nm_500_MHz_2022-03-22-20-43_2947df5b/reports/wallypipelinedcore_power.rep" (CMD-015)
|
||||
set filename [format "%s%s%s%s" $outputDir "/reports/" $my_toplevel "_constraint.rep"]
|
||||
runs/wallypipelinedcore_rv32e_sky90 nm_500_MHz_2022-03-22-20-43_2947df5b/reports/wallypipelinedcore_constraint.rep
|
||||
redirect $filename { report_constraint }
|
||||
Error: could not open output redirect file "runs/wallypipelinedcore_rv32e_sky90 nm_500_MHz_2022-03-22-20-43_2947df5b/reports/wallypipelinedcore_constraint.rep" (CMD-015)
|
||||
set filename [format "%s%s%s%s" $outputDir "/reports/" $my_toplevel "_hier.rep"]
|
||||
runs/wallypipelinedcore_rv32e_sky90 nm_500_MHz_2022-03-22-20-43_2947df5b/reports/wallypipelinedcore_hier.rep
|
||||
# redirect $filename { report_hierarchy }
|
||||
quit
|
||||
|
||||
Memory usage for this session 101 Mbytes.
|
||||
Memory usage for this session including child processes 101 Mbytes.
|
||||
CPU usage for this session 7 seconds ( 0.00 hours ).
|
||||
Elapsed time for this session 9 seconds ( 0.00 hours ).
|
||||
|
||||
Thank you...
|
||||
@ -1,135 +0,0 @@
|
||||
//////////////////////////////////////////
|
||||
// wally-config.vh
|
||||
//
|
||||
// Written: David_Harris@hmc.edu 4 January 2021
|
||||
// Modified:
|
||||
//
|
||||
// Purpose: Specify which features are configured
|
||||
// Macros to determine which modes are supported based on MISA
|
||||
//
|
||||
// A component of the Wally configurable RISC-V project.
|
||||
//
|
||||
// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
|
||||
//
|
||||
// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
|
||||
// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy,
|
||||
// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software
|
||||
// is furnished to do so, subject to the following conditions:
|
||||
//
|
||||
// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
|
||||
//
|
||||
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
|
||||
// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
|
||||
// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
|
||||
// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||||
///////////////////////////////////////////
|
||||
|
||||
// include shared configuration
|
||||
`include "wally-shared.vh"
|
||||
|
||||
`define FPGA 0
|
||||
`define QEMU 0
|
||||
`define DESIGN_COMPILER 0
|
||||
|
||||
// RV32 or RV64: XLEN = 32 or 64
|
||||
`define XLEN 32
|
||||
|
||||
// IEEE 754 compliance
|
||||
`define IEEE754 0
|
||||
|
||||
// E
|
||||
`define MISA (32'h00000010)
|
||||
`define ZICSR_SUPPORTED 0
|
||||
`define ZIFENCEI_SUPPORTED 0
|
||||
`define COUNTERS 0
|
||||
`define ZICOUNTERS_SUPPORTED 0
|
||||
|
||||
// Microarchitectural Features
|
||||
`define UARCH_PIPELINED 1
|
||||
`define UARCH_SUPERSCALR 0
|
||||
`define UARCH_SINGLECYCLE 0
|
||||
// *** replace with MEM_BUS
|
||||
`define DMEM `MEM_NONE
|
||||
`define IMEM `MEM_NONE
|
||||
`define DBUS 1
|
||||
`define IBUS 1
|
||||
`define VIRTMEM_SUPPORTED 0
|
||||
`define VECTORED_INTERRUPTS_SUPPORTED 0
|
||||
|
||||
// TLB configuration. Entries should be a power of 2
|
||||
`define ITLB_ENTRIES 0
|
||||
`define DTLB_ENTRIES 0
|
||||
|
||||
// Cache configuration. Sizes should be a power of two
|
||||
// typical configuration 4 ways, 4096 bytes per way, 256 bit or more lines
|
||||
`define DCACHE_NUMWAYS 4
|
||||
`define DCACHE_WAYSIZEINBYTES 4096
|
||||
`define DCACHE_LINELENINBITS 256
|
||||
`define ICACHE_NUMWAYS 4
|
||||
`define ICACHE_WAYSIZEINBYTES 4096
|
||||
`define ICACHE_LINELENINBITS 256
|
||||
|
||||
// Integer Divider Configuration
|
||||
// DIV_BITSPERCYCLE must be 1, 2, or 4
|
||||
`define DIV_BITSPERCYCLE 1
|
||||
|
||||
// Legal number of PMP entries are 0, 16, or 64
|
||||
`define PMP_ENTRIES 0
|
||||
|
||||
// Address space
|
||||
`define RESET_VECTOR 32'h80000000
|
||||
|
||||
// Peripheral Addresses
|
||||
// Peripheral memory space extends from BASE to BASE+RANGE
|
||||
// Range should be a thermometer code with 0's in the upper bits and 1s in the lower bits
|
||||
`define BOOTROM_SUPPORTED 1'b1
|
||||
`define BOOTROM_BASE 34'h00001000
|
||||
`define BOOTROM_RANGE 34'h00000FFF
|
||||
`define RAM_SUPPORTED 1'b1
|
||||
`define RAM_BASE 34'h80000000
|
||||
`define RAM_RANGE 34'h07FFFFFF
|
||||
`define EXT_MEM_SUPPORTED 1'b0
|
||||
`define EXT_MEM_BASE 34'h80000000
|
||||
`define EXT_MEM_RANGE 34'h07FFFFFF
|
||||
`define CLINT_SUPPORTED 1'b0
|
||||
`define CLINT_BASE 34'h02000000
|
||||
`define CLINT_RANGE 34'h0000FFFF
|
||||
`define GPIO_SUPPORTED 1'b0
|
||||
`define GPIO_BASE 34'h10060000
|
||||
`define GPIO_RANGE 34'h000000FF
|
||||
`define UART_SUPPORTED 1'b0
|
||||
`define UART_BASE 34'h10000000
|
||||
`define UART_RANGE 34'h00000007
|
||||
`define PLIC_SUPPORTED 1'b0
|
||||
`define PLIC_BASE 34'h0C000000
|
||||
`define PLIC_RANGE 34'h03FFFFFF
|
||||
`define SDC_SUPPORTED 1'b0
|
||||
`define SDC_BASE 34'h00012100
|
||||
`define SDC_RANGE 34'h0000001F
|
||||
|
||||
// Bus Interface width
|
||||
`define AHBW 32
|
||||
|
||||
// Test modes
|
||||
|
||||
// Tie GPIO outputs back to inputs
|
||||
`define GPIO_LOOPBACK_TEST 1
|
||||
|
||||
// Hardware configuration
|
||||
`define UART_PRESCALE 1
|
||||
|
||||
// Interrupt configuration
|
||||
`define PLIC_NUM_SRC 10
|
||||
// comment out the following if >=32 sources
|
||||
`define PLIC_NUM_SRC_LT_32
|
||||
`define PLIC_GPIO_ID 3
|
||||
`define PLIC_UART_ID 10
|
||||
|
||||
`define TWO_BIT_PRELOAD "../config/rv32ic/twoBitPredictor.txt"
|
||||
`define BTB_PRELOAD "../config/rv32ic/BTBPredictor.txt"
|
||||
`define BPRED_ENABLED 0
|
||||
`define BPTYPE "BPGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE
|
||||
`define TESTSBP 0
|
||||
|
||||
`define REPLAY 0
|
||||
`define HPTW_WRITES_SUPPORTED 0
|
||||
@ -2,6 +2,7 @@
|
||||
# Madeleine Masser-Frye mmasserfrye@hmc.edu 5/22
|
||||
|
||||
from operator import index
|
||||
import scipy.optimize as opt
|
||||
import subprocess
|
||||
import csv
|
||||
import re
|
||||
@ -11,14 +12,14 @@ import matplotlib.lines as lines
|
||||
import matplotlib.axes as axes
|
||||
import numpy as np
|
||||
from collections import namedtuple
|
||||
|
||||
import sklearn.metrics as skm
|
||||
|
||||
def synthsfromcsv(filename):
|
||||
Synth = namedtuple("Synth", "module tech width freq delay area lpower denergy")
|
||||
with open(filename, newline='') as csvfile:
|
||||
csvreader = csv.reader(csvfile)
|
||||
global allSynths
|
||||
allSynths = list(csvreader)
|
||||
allSynths = list(csvreader)[1:]
|
||||
for i in range(len(allSynths)):
|
||||
for j in range(len(allSynths[0])):
|
||||
try: allSynths[i][j] = int(allSynths[i][j])
|
||||
@ -26,6 +27,7 @@ def synthsfromcsv(filename):
|
||||
try: allSynths[i][j] = float(allSynths[i][j])
|
||||
except: pass
|
||||
allSynths[i] = Synth(*allSynths[i])
|
||||
return allSynths
|
||||
|
||||
def synthsintocsv():
|
||||
''' writes a CSV with one line for every available synthesis
|
||||
@ -37,28 +39,32 @@ def synthsintocsv():
|
||||
allSynths = output.decode("utf-8").split('\n')[:-1]
|
||||
|
||||
specReg = re.compile('[a-zA-Z0-9]+')
|
||||
metricReg = re.compile('\d+\.\d+[e]?[-+]?\d*')
|
||||
metricReg = re.compile('-?\d+\.\d+[e]?[-+]?\d*')
|
||||
|
||||
file = open("ppaData.csv", "w")
|
||||
writer = csv.writer(file)
|
||||
writer.writerow(['Module', 'Tech', 'Width', 'Target Freq', 'Delay', 'Area', 'L Power (nW)', 'D energy (mJ)'])
|
||||
writer.writerow(['Module', 'Tech', 'Width', 'Target Freq', 'Delay', 'Area', 'L Power (nW)', 'D energy (fJ)'])
|
||||
|
||||
for oneSynth in allSynths:
|
||||
module, width, risc, tech, freq = specReg.findall(oneSynth)[2:7]
|
||||
tech = tech[:-2]
|
||||
metrics = []
|
||||
for phrase in [['Path Length', 'qor'], ['Design Area', 'qor'], ['100', 'power']]:
|
||||
for phrase in [['Path Slack', 'qor'], ['Clk Period', 'qor'], ['Design Area', 'qor'], ['100', 'power']]:
|
||||
bashCommand = 'grep "{}" '+ oneSynth[2:]+'/reports/*{}*'
|
||||
bashCommand = bashCommand.format(*phrase)
|
||||
try: output = subprocess.check_output(['bash','-c', bashCommand])
|
||||
except: print("At least one synth run doesn't have reports, try cleanup() first")
|
||||
except:
|
||||
print(module + width + tech + freq + " doesn't have reports")
|
||||
print("Consider running cleanup() first")
|
||||
nums = metricReg.findall(str(output))
|
||||
nums = [float(m) for m in nums]
|
||||
metrics += nums
|
||||
delay = metrics[0]
|
||||
area = metrics[1]
|
||||
lpower = metrics[4]
|
||||
denergy = (metrics[2] + metrics[3])*delay # (switching + internal powers)*delay
|
||||
delay = metrics[1] - metrics[0]
|
||||
area = metrics[2]
|
||||
lpower = metrics[5]
|
||||
denergy = (metrics[3] + metrics[4])*delay*1000 # (switching + internal powers)*delay, more practical units for regression coefs
|
||||
|
||||
if ('flop' in module): area = area/2 # since two flops in each module
|
||||
|
||||
writer.writerow([module, tech, width, freq, delay, area, lpower, denergy])
|
||||
file.close()
|
||||
@ -119,13 +125,31 @@ def getVals(tech, module, var, freq=None):
|
||||
try: metric += [met]
|
||||
except: pass
|
||||
|
||||
if ('flop' in module) & (var == 'area'):
|
||||
metric = [m/2 for m in metric] # since two flops in each module
|
||||
if (var == 'denergy'):
|
||||
metric = [m*1000 for m in metric] # more practical units for regression coefs
|
||||
|
||||
return metric
|
||||
|
||||
def csvOfBest():
|
||||
global techSpecs, widths, modules, allSynths
|
||||
bestSynths = []
|
||||
for tech in [x.tech for x in techSpecs]:
|
||||
for mod in modules:
|
||||
for w in widths:
|
||||
m = 100000 # large number to start
|
||||
best = None
|
||||
for oneSynth in allSynths:
|
||||
if (oneSynth.width == w) & (oneSynth.tech == tech) & (oneSynth.module == mod):
|
||||
if (oneSynth.delay < m) & (1000/oneSynth.delay > oneSynth.freq):
|
||||
m = oneSynth.delay
|
||||
best = oneSynth
|
||||
if (best != None) & (best not in bestSynths):
|
||||
bestSynths += [best]
|
||||
|
||||
file = open("bestSynths.csv", "w")
|
||||
writer = csv.writer(file)
|
||||
writer.writerow(['Module', 'Tech', 'Width', 'Target Freq', 'Delay', 'Area', 'L Power (nW)', 'D energy (fJ)'])
|
||||
for synth in bestSynths:
|
||||
writer.writerow(list(synth))
|
||||
file.close()
|
||||
|
||||
def genLegend(fits, coefs, r2, spec):
|
||||
''' generates a list of two legend elements
|
||||
labels line with fit equation and dots with tech and r squared of the fit
|
||||
@ -135,21 +159,15 @@ def genLegend(fits, coefs, r2, spec):
|
||||
|
||||
eq = ''
|
||||
ind = 0
|
||||
if 'c' in fits:
|
||||
eq += coefsr[ind]
|
||||
ind += 1
|
||||
if 'l' in fits:
|
||||
eq += " + " + coefsr[ind] + "*N"
|
||||
ind += 1
|
||||
if 's' in fits:
|
||||
eq += " + " + coefsr[ind] + "*N^2"
|
||||
ind += 1
|
||||
if 'g' in fits:
|
||||
eq += " + " + coefsr[ind] + "*log2(N)"
|
||||
ind += 1
|
||||
if 'n' in fits:
|
||||
eq += " + " + coefsr[ind] + "*Nlog2(N)"
|
||||
ind += 1
|
||||
|
||||
eqDict = {'c': '', 'l': 'N', 's': '$N^2$', 'g': '$log_2$(N)', 'n': 'N$log_2$(N)'}
|
||||
|
||||
for k in eqDict.keys():
|
||||
if k in fits:
|
||||
if str(coefsr[ind]) != '0.0': eq += " + " + coefsr[ind] + eqDict[k]
|
||||
ind += 1
|
||||
|
||||
eq = eq[3:]
|
||||
|
||||
legend_elements = [lines.Line2D([0], [0], color=spec.color, label=eq),
|
||||
lines.Line2D([0], [0], color=spec.color, ls='', marker=spec.shape, label=spec.tech +' $R^2$='+ str(round(r2, 4)))]
|
||||
@ -196,9 +214,9 @@ def oneMetricPlot(module, var, freq=None, ax=None, fits='clsgn', norm=True, colo
|
||||
ax.set_xlabel("Width (bits)")
|
||||
|
||||
if norm:
|
||||
ylabeldic = {"lpower": "Normalized Leakage Power", "denergy": "Normalized Dynamic Energy", "area": "INVx1 Areas", "delay": "FO4 Delays"}
|
||||
ylabeldic = {"lpower": "Leakage Power (add32)", "denergy": "Energy/Op (add32)", "area": "Area (add32)", "delay": "Delay (FO4)"}
|
||||
else:
|
||||
ylabeldic = {"lpower": "Leakage Power (nW)", "denergy": "Dynamic Energy (nJ)", "area": "Area (sq microns)", "delay": "Delay (ns)"}
|
||||
ylabeldic = {"lpower": "Leakage Power (nW)", "denergy": "Dynamic Energy (fJ)", "area": "Area (sq microns)", "delay": "Delay (ns)"}
|
||||
|
||||
ax.set_ylabel(ylabeldic[var])
|
||||
|
||||
@ -206,7 +224,7 @@ def oneMetricPlot(module, var, freq=None, ax=None, fits='clsgn', norm=True, colo
|
||||
titleStr = " (target " + str(freq)+ "MHz)" if freq != None else " (best achievable delay)"
|
||||
ax.set_title(module + titleStr)
|
||||
plt.savefig('./plots/PPA/'+ module + '_' + var + '.png')
|
||||
# plt.show()
|
||||
plt.show()
|
||||
|
||||
def regress(widths, var, spec, fits='clsgn'):
|
||||
''' fits a curve to the given points
|
||||
@ -223,20 +241,22 @@ def regress(widths, var, spec, fits='clsgn'):
|
||||
mat += [row]
|
||||
|
||||
y = np.array(var, dtype=np.float)
|
||||
coefsResid = np.linalg.lstsq(mat, y, rcond=None)
|
||||
coefsResid = opt.nnls(mat, y)
|
||||
coefs = coefsResid[0]
|
||||
try:
|
||||
resid = coefsResid[1][0]
|
||||
r2 = 1 - resid / (y.size * y.var())
|
||||
except:
|
||||
r2 = 0
|
||||
|
||||
xp = np.linspace(8, 140, 200)
|
||||
xp = np.linspace(4, 140, 200)
|
||||
pred = []
|
||||
yp = []
|
||||
for x in xp:
|
||||
n = [func(x) for func in funcArr]
|
||||
pred += [sum(np.multiply(coefs, n))]
|
||||
|
||||
for w in widths:
|
||||
n = [func(w) for func in funcArr]
|
||||
yp += [sum(np.multiply(coefs, n))]
|
||||
|
||||
r2 = skm.r2_score(y, yp)
|
||||
|
||||
leg = genLegend(fits, coefs, r2, spec)
|
||||
|
||||
return xp, pred, leg
|
||||
@ -287,14 +307,17 @@ def noOutliers(freqs, delays, areas):
|
||||
f=[]
|
||||
d=[]
|
||||
a=[]
|
||||
ind = delays.index(min(delays))
|
||||
med = freqs[ind]
|
||||
for i in range(len(freqs)):
|
||||
norm = freqs[i]/med
|
||||
if (norm > 0.25) & (norm<1.75):
|
||||
f += [freqs[i]]
|
||||
d += [delays[i]]
|
||||
a += [areas[i]]
|
||||
try:
|
||||
ind = delays.index(min(delays))
|
||||
med = freqs[ind]
|
||||
for i in range(len(freqs)):
|
||||
norm = freqs[i]/med
|
||||
# if (norm > 0.25) & (norm<1.75):
|
||||
if freqs[i] < 8000:
|
||||
f += [freqs[i]]
|
||||
d += [delays[i]]
|
||||
a += [areas[i]]
|
||||
except: pass
|
||||
|
||||
return f, d, a
|
||||
|
||||
@ -303,14 +326,18 @@ def freqPlot(tech, mod, width):
|
||||
'''
|
||||
global allSynths
|
||||
freqsL, delaysL, areasL = ([[], []] for i in range(3))
|
||||
count = 0
|
||||
for oneSynth in allSynths:
|
||||
if (mod == oneSynth.module) & (width == oneSynth.width) & (tech == oneSynth.tech):
|
||||
count += 1
|
||||
ind = (1000/oneSynth.delay < oneSynth.freq) # when delay is within target clock period
|
||||
freqsL[ind] += [oneSynth.freq]
|
||||
delaysL[ind] += [oneSynth.delay]
|
||||
areasL[ind] += [oneSynth.area]
|
||||
|
||||
|
||||
f, (ax1, ax2, ax3, ax4) = plt.subplots(4, 1, sharex=True)
|
||||
for ax in (ax1, ax2, ax3, ax4):
|
||||
ax.ticklabel_format(useOffset=False, style='plain')
|
||||
|
||||
for ind in [0,1]:
|
||||
areas = areasL[ind]
|
||||
@ -339,7 +366,7 @@ def freqPlot(tech, mod, width):
|
||||
ax3.set_ylabel('Area * Delay')
|
||||
ax4.set_ylabel('Area * $Delay^2$')
|
||||
ax1.set_title(mod + '_' + str(width))
|
||||
plt.savefig('./plots/freqBuckshot/' + mod + '/' + str(width) + '.png')
|
||||
plt.savefig('./plots/freqBuckshot/' + tech + '/' + mod + '/' + str(width) + '.png')
|
||||
# plt.show()
|
||||
|
||||
def squareAreaDelay(tech, mod, width):
|
||||
@ -433,6 +460,7 @@ def plotPPA(mod, freq=None, norm=True):
|
||||
if no freq specified, uses the synthesis with best achievable delay for each width
|
||||
overlays data from both techs
|
||||
'''
|
||||
plt.rcParams["figure.figsize"] = (12,8)
|
||||
fig, axs = plt.subplots(2, 2)
|
||||
global fitDict
|
||||
modFit = fitDict[mod]
|
||||
@ -447,44 +475,57 @@ def plotPPA(mod, freq=None, norm=True):
|
||||
plt.savefig(saveStr)
|
||||
# plt.show()
|
||||
|
||||
def plotBestAreas():
|
||||
global fitDict
|
||||
def plotBestAreas(mod):
|
||||
fig, axs = plt.subplots(1, 1)
|
||||
mods = ['priorityencoder', 'add', 'csa', 'shiftleft', 'comparator', 'flop']
|
||||
colors = ['red', 'orange', 'yellow', 'green', 'blue', 'purple']
|
||||
legend_elements = []
|
||||
for i in range(len(mods)):
|
||||
oneMetricPlot(mods[i], 'area', ax=axs, freq=10, norm=False, color=colors[i])
|
||||
legend_elements += [lines.Line2D([0], [0], color=colors[i], ls='', marker='o', label=mods[i])]
|
||||
plt.suptitle('Optimized Areas (target freq 10MHz)')
|
||||
plt.legend(handles=legend_elements)
|
||||
plt.savefig('./plots/bestareas.png')
|
||||
### all areas on one
|
||||
# mods = ['priorityencoder', 'add', 'csa', 'shiftleft', 'comparator', 'flop']
|
||||
# colors = ['red', 'orange', 'yellow', 'green', 'blue', 'purple']
|
||||
# legend_elements = []
|
||||
# for i in range(len(mods)):
|
||||
# oneMetricPlot(mods[i], 'area', ax=axs, freq=10, norm=False, color=colors[i])
|
||||
# legend_elements += [lines.Line2D([0], [0], color=colors[i], ls='', marker='o', label=mods[i])]
|
||||
# plt.suptitle('Optimized Areas (target freq 10MHz)')
|
||||
# plt.legend(handles=legend_elements)
|
||||
# plt.savefig('./plots/bestareas.png')
|
||||
# plt.show()
|
||||
|
||||
oneMetricPlot(mod, 'area', freq=10)
|
||||
plt.title(mod + ' Optimized Areas (target freq 10MHz)')
|
||||
plt.savefig('./plots/bestAreas/' + mod + '.png')
|
||||
|
||||
if __name__ == '__main__':
|
||||
|
||||
# set up stuff, global variables
|
||||
widths = [8, 16, 32, 64, 128]
|
||||
# fitDict in progress
|
||||
fitDict = {'add': ['gl', 'lg'], 'mult': ['clg', 's'], 'comparator': ['clsgn', 'clsgn'], 'csa': ['clsgn', 'clsgn'], 'shiftleft': ['clsgn', 'clsgn'], 'flop': ['cl', 'cl'], 'priorityencoder': ['clsgn', 'clsgn']}
|
||||
fitDict = {'add': ['cg', 'l', 'l'], 'mult': ['cg', 'sl', 'ls'], 'comparator': ['cg', 'l', 'l'], 'csa': ['c', 'l', 'l'], 'shiftleft': ['cg', 'n', 'ln'], 'flop': ['c', 'l', 'l'], 'priorityencoder': ['cg', 'l', 'l']}
|
||||
fitDict.update(dict.fromkeys(['mux2', 'mux4', 'mux8'], ['cg', 'l', 'l'])) #data
|
||||
TechSpec = namedtuple("TechSpec", "tech color shape delay area lpower denergy")
|
||||
techSpecs = [['sky90', 'green', 'o', 43.2e-3, 1.96, 1.98, 1], ['gf32', 'purple', 's', 15e-3, .351, .3116, 1], ['tsmc28', 'blue', '^', 12.2e-3, .252, 1.09, 1]]
|
||||
techSpecs = [['sky90', 'green', 'o', 43.2e-3, 1330.84, 582.81, 520.66], ['tsmc28', 'blue', '^', 12.2e-3, 209.29, 1060, 81.43]]
|
||||
|
||||
invz1arealeakage = [['sky90', 1.96, 1.98], ['gf32', .351, .3116], ['tsmc28', .252, 1.09]] #['gf32', 'purple', 's', 15e-3]
|
||||
techSpecs = [TechSpec(*t) for t in techSpecs]
|
||||
modules = ['priorityencoder', 'add', 'csa', 'shiftleft', 'comparator', 'flop', 'mux2', 'mux4', 'mux8', 'mult']
|
||||
|
||||
|
||||
# cleanup()
|
||||
# synthsintocsv() # slow, run only when new synth runs to add to csv
|
||||
|
||||
synthsfromcsv('ppaData.csv') # your csv here!
|
||||
allSynths = synthsfromcsv('ppaData.csv') # your csv here!
|
||||
|
||||
# ### examples
|
||||
# # ### examples
|
||||
|
||||
# squareAreaDelay('sky90', 'add', 32)
|
||||
# oneMetricPlot('add', 'delay')
|
||||
plotBestAreas()
|
||||
# # squareAreaDelay('sky90', 'add', 32)
|
||||
# # plotBestAreas('add')
|
||||
# oneMetricPlot('mux2', 'delay', norm=False)
|
||||
# print(len(freqsL[0]))
|
||||
# freqPlot('sky90', 'mux4', 16)
|
||||
|
||||
mods = ['priorityencoder', 'add', 'csa', 'shiftleft', 'comparator', 'flop', 'mult']
|
||||
for mod in mods:
|
||||
for mod in modules:
|
||||
plotPPA(mod, norm=False)
|
||||
plotPPA(mod)
|
||||
for w in [8, 16, 32, 64, 128]:
|
||||
freqPlot('sky90', mod, w)
|
||||
freqPlot('sky90', mod, w)
|
||||
freqPlot('tsmc28', mod, w)
|
||||
plt.close('all')
|
||||
|
||||
csvOfBest()
|
||||
3233
synthDC/ppaData.csv
3233
synthDC/ppaData.csv
File diff suppressed because it is too large
Load Diff
1439
synthDC/ppaDataOld.csv
Normal file
1439
synthDC/ppaDataOld.csv
Normal file
File diff suppressed because it is too large
Load Diff
@ -1,9 +1,12 @@
|
||||
#!/usr/bin/python3
|
||||
# Madeleine Masser-Frye mmasserfrye@hmc.edu 5/22
|
||||
|
||||
from collections import namedtuple
|
||||
import csv
|
||||
import subprocess
|
||||
import re
|
||||
from multiprocessing import Pool
|
||||
from multiprocessing import Pool, cpu_count
|
||||
from ppaAnalyze import synthsfromcsv
|
||||
|
||||
|
||||
def runCommand(module, width, tech, freq):
|
||||
@ -17,59 +20,59 @@ def deleteRedundant(LoT):
|
||||
bashCommand = synthStr.format(*synth)
|
||||
outputCPL = subprocess.check_output(['bash','-c', bashCommand])
|
||||
|
||||
def getData():
|
||||
bashCommand = "grep 'Critical Path Length' runs/ppa_*/reports/*qor*"
|
||||
outputCPL = subprocess.check_output(['bash','-c', bashCommand])
|
||||
linesCPL = outputCPL.decode("utf-8").split('\n')[:-1]
|
||||
def getData(filename):
|
||||
Synth = namedtuple("Synth", "module tech width freq delay area lpower denergy")
|
||||
with open(filename, newline='') as csvfile:
|
||||
csvreader = csv.reader(csvfile)
|
||||
global allSynths
|
||||
allSynths = list(csvreader)
|
||||
for i in range(len(allSynths)):
|
||||
for j in range(len(allSynths[0])):
|
||||
try: allSynths[i][j] = int(allSynths[i][j])
|
||||
except:
|
||||
try: allSynths[i][j] = float(allSynths[i][j])
|
||||
except: pass
|
||||
allSynths[i] = Synth(*allSynths[i])
|
||||
|
||||
cpl = re.compile('\d{1}\.\d{6}')
|
||||
f = re.compile('_\d*_MHz')
|
||||
wm = re.compile('ppa_\w*_\d*_qor')
|
||||
|
||||
allSynths = []
|
||||
# arr = [-5, -3, -1, 1, 3, 5]
|
||||
arr2 = [-8, -6, -4, -2, 0, 2, 4, 6, 8]
|
||||
|
||||
for i in range(len(linesCPL)):
|
||||
line = linesCPL[i]
|
||||
mwm = wm.findall(line)[0][4:-4].split('_')
|
||||
freq = int(f.findall(line)[0][1:-4])
|
||||
delay = float(cpl.findall(line)[0])
|
||||
mod = mwm[0]
|
||||
width = int(mwm[1])
|
||||
|
||||
oneSynth = [mod, width, freq, delay]
|
||||
allSynths += [oneSynth]
|
||||
|
||||
return allSynths
|
||||
|
||||
allSynths = getData()
|
||||
arr = [-40, -20, -8, -6, -4, -2, 0, 2, 4, 6, 8, 12, 20, 40]
|
||||
|
||||
widths = [16, 8, 32, 64, 128]
|
||||
modules = ['add']
|
||||
tech = 'tsmc28'
|
||||
widths = [32]
|
||||
modules = ['mux2']#, 'comparator'] #, 'mux2', 'mux4', 'mux8', 'shiftleft', 'flop', 'comparator'] # need mult, 'shiftleft', add
|
||||
techs = ['sky90']
|
||||
LoT = []
|
||||
|
||||
# # # initial sweep to get estimate of min delay
|
||||
# freqs = [25000, 35000]
|
||||
# for module in modules:
|
||||
# for width in widths:
|
||||
# for freq in freqs:
|
||||
# LoT += [[module, width, tech, freq]]
|
||||
|
||||
allSynths = synthsfromcsv('ppaData.csv')
|
||||
|
||||
for w in widths:
|
||||
for module in modules:
|
||||
for tech in techs:
|
||||
m = 100000 # large number to start
|
||||
for oneSynth in allSynths:
|
||||
if (oneSynth.width == w) & (oneSynth.tech == tech) & (oneSynth.module == module):
|
||||
if (oneSynth.delay < m):
|
||||
m = oneSynth.delay
|
||||
synth = oneSynth
|
||||
# f = 1000/synth.delay
|
||||
f = 4950
|
||||
for freq in [round(f+f*x/100) for x in arr2]:
|
||||
LoT += [[synth.module, str(synth.width), synth.tech, str(freq)]]
|
||||
|
||||
|
||||
# # thorough sweep based on estimate of min delay
|
||||
for m in modules:
|
||||
for w in widths:
|
||||
delays = []
|
||||
for oneSynth in allSynths:
|
||||
if (oneSynth[0] == m) & (oneSynth[1] == w):
|
||||
delays += [oneSynth[3]]
|
||||
try: f = 1000/min(delays)
|
||||
except: print(m)
|
||||
for freq in [str(round(f+f*x/100)) for x in arr]:
|
||||
LoT += [[m, w, tech, freq]]
|
||||
bashCommand = "find . -path '*runs/ppa*rv32e*' -prune"
|
||||
output = subprocess.check_output(['bash','-c', bashCommand])
|
||||
specReg = re.compile('[a-zA-Z0-9]+')
|
||||
allSynths = output.decode("utf-8").split('\n')[:-1]
|
||||
allSynths = [specReg.findall(oneSynth)[2:7] for oneSynth in allSynths]
|
||||
allSynths = [oneSynth[0:2] + [oneSynth[3][:-2]] + [oneSynth[4]] for oneSynth in allSynths]
|
||||
|
||||
deleteRedundant(LoT)
|
||||
pool = Pool()
|
||||
pool.starmap(runCommand, LoT)
|
||||
synthsToRun = []
|
||||
for synth in LoT:
|
||||
if synth not in allSynths:
|
||||
synthsToRun += [synth]
|
||||
|
||||
pool = Pool(processes=25)
|
||||
pool.starmap(runCommand, synthsToRun)
|
||||
pool.close()
|
||||
@ -367,4 +367,4 @@ redirect $filename { report_constraint }
|
||||
set filename [format "%s%s%s%s" $outputDir "/reports/" $my_toplevel "_hier.rep"]
|
||||
# redirect $filename { report_hierarchy }
|
||||
|
||||
#quit
|
||||
quit
|
||||
|
||||
Loading…
Reference in New Issue
Block a user