forked from Github_Repos/cvw
Clean up sqrt initialization mux
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@ -51,20 +51,14 @@ module fdivsqrtpreproc (
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);
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logic [`DIVb-1:0] XPreproc;
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logic [`DIVb:0] SqrtX;
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logic [`DIVb+3:0] DivX;
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logic [`DIVb:0] PreSqrtX;
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logic [`DIVb+3:0] DivX, SqrtX;
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logic [`NE+1:0] QeE;
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// Intdiv signals
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logic [`DIVb-1:0] IFNormLenX, IFNormLenD;
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logic [`DIVBLEN:0] mE;
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logic [`DIVBLEN:0] pPlusr, pPrCeil, p, ell;
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logic [`LOGRK:0] pPrTrunc;
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logic [`DIVBLEN:0] mE, ell;
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logic [`DIVb+3:0] PreShiftX;
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logic NumZeroE;
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// ***can probably merge X LZC with conversion
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// cout the number of leading zeros
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if (`IDIV_ON_FPU) begin
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logic signedDiv;
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logic AsE, BsE, ALTBE, NegQuotE;
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@ -72,6 +66,8 @@ module fdivsqrtpreproc (
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logic [`XLEN-1:0] PosA, PosB;
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logic [`DIVBLEN:0] ZeroDiff, IntBits;
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logic [`LOGRK-1:0] RightShiftX;
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logic [`DIVBLEN:0] pPlusr, pPrCeil, p;
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logic [`LOGRK-1:0] pPrTrunc;
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// Extract inputs, signs, zero, depending on W64 mode if applicable
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assign signedDiv = ~Funct3E[0];
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@ -149,16 +145,15 @@ module fdivsqrtpreproc (
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assign DPreproc = IFNormLenD << (mE + {{`DIVBLEN{1'b0}}, 1'b1});
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// append leading 1 (for nonzero inputs) and zero-extend
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assign SqrtX = (Xe[0]^ell[0]) ? {1'b0, ~NumZeroE, XPreproc[`DIVb-1:1]} : {~NumZeroE, XPreproc}; // Bottom bit of XPreproc is always zero because DIVb is larger than XLEN and NF
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assign PreSqrtX = (Xe[0]^ell[0]) ? {1'b0, ~NumZeroE, XPreproc[`DIVb-1:1]} : {~NumZeroE, XPreproc}; // Bottom bit of XPreproc is always zero because DIVb is larger than XLEN and NF
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assign DivX = {3'b000, ~NumZeroE, XPreproc};
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// *** explain why X is shifted between radices (initial assignment of WS=RX)
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if (`RADIX == 2) assign PreShiftX = Sqrt ? {3'b111, SqrtX} : DivX;
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else assign PreShiftX = Sqrt ? {2'b11, SqrtX, 1'b0} : DivX;
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// Sqrt is initialized after a first step of R(X-1), which depends on Radix
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if (`RADIX == 2) assign SqrtX = {3'b111, PreSqrtX};
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else assign SqrtX = {2'b11, PreSqrtX, 1'b0};
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assign PreShiftX = Sqrt ? SqrtX : DivX;
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// Floating-point exponent
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fdivsqrtexpcalc expcalc(.Fmt, .Xe, .Ye, .Sqrt, .XZero(XZeroE), .ell, .m(mE), .Qe(QeE));
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flopen #(`NE+2) expreg(clk, IFDivStartE, QeE, QeM);
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flopen #(`NE+2) expreg(clk, IFDivStartE, QeE, QeM);
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endmodule
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