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config file, comment, postproc cleanup

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This commit is contained in:
David Harris 2022-12-31 05:20:56 -08:00
parent 0836d4d4f0
commit 6832b9d9f6
4 changed files with 11 additions and 44 deletions
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31
pipelined/config/shared/wally-shared.vh
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@ -26,8 +26,6 @@
`include "wally-constants.vh"
// macros to define supported modes
// NOTE: No hardware support for Q yet
`define A_SUPPORTED ((`MISA >> 0) % 2 == 1)
`define C_SUPPORTED ((`MISA >> 2) % 2 == 1)
`define D_SUPPORTED ((`MISA >> 3) % 2 == 1)
@ -38,11 +36,7 @@
`define Q_SUPPORTED ((`MISA >> 16) % 2 == 1)
`define S_SUPPORTED ((`MISA >> 18) % 2 == 1)
`define U_SUPPORTED ((`MISA >> 20) % 2 == 1)
// N-mode user-level interrupts are depricated per Andrew Waterman 1/13/21
//`define N_SUPPORTED ((MISA >> 13) % 2 == 1)
`define N_SUPPORTED 0
// logarithm of XLEN, used for number of index bits to select
`define LOG_XLEN (`XLEN == 32 ? 5 : 6)
@ -108,30 +102,6 @@
`define LOGNORMSHIFTSZ ($clog2(`NORMSHIFTSZ))
`define CORRSHIFTSZ ((`DIVRESLEN+`NF) > (3*`NF+6) ? (`DIVRESLEN+`NF) : (3*`NF+4))
/*
// division constants
`define RADIX 32'h4
`define DIVCOPIES 32'h4
`define DIVLEN ((`NF < `XLEN) ? (`XLEN) : `NF+3)
// `define DIVN (`NF < `XLEN ? `XLEN : `NF+1) // length of input
`define DIVN (`NF<`XLEN ? `XLEN : (`NF + 3)) // length of input
`define EXTRAFRACBITS ((`NF < (`XLEN)) ? (`XLEN - `NF) : 3)
`define EXTRAINTBITS ((`NF < `XLEN) ? 0 : (`NF - `XLEN + 3))
`define DIVRESLEN ((`NF>`XLEN) ? (`NF + 4) : `XLEN)
`define LOGR ((`RADIX==2) ? 32'h1 : 32'h2)
`define RK (`DIVCOPIES*`LOGR) // r*k used for intdiv preproc
`define LOGK ($clog2(`DIVCOPIES))
`define LOGRK ($clog2(`RK)) // log2(r*k)
// FPDUR = ceil(DIVRESLEN/(LOGR*DIVCOPIES))
// one iteration is required for the integer bit for minimally redundent radix-4
`define FPDUR ((`DIVN+1+(`LOGR*`DIVCOPIES))/(`LOGR*`DIVCOPIES)+(`RADIX/4))
`define DURLEN ($clog2(`FPDUR+1))
`define QLEN (`FPDUR*`LOGR*`DIVCOPIES)
`define DIVb (`QLEN-1)
`define DIVa (`DIVb+1-`XLEN)
`define DIVBLEN ($clog2(`DIVb+1)-1)
*/
// division constants
`define RADIX 32'h4
`define DIVCOPIES 32'h4
@ -147,7 +117,6 @@
`define DIVBLEN ($clog2(`DIVb+1)-1)
`define DIVa (`DIVb+1-`XLEN) // used for idiv on fpu
`define USE_SRAM 0
// Disable spurious Verilator warnings

4
pipelined/src/fpu/fdivsqrt/fdivsqrt.sv
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@ -44,16 +44,14 @@ module fdivsqrt(
input logic StallM,
input logic FlushE,
input logic SqrtE, SqrtM,
input logic [`XLEN-1:0] ForwardedSrcAE, ForwardedSrcBE, // *** these are the src outputs before the mux choosing between them and PCE to put in srcA/B
input logic [`XLEN-1:0] ForwardedSrcAE, ForwardedSrcBE, // these are the src outputs before the mux choosing between them and PCE to put in srcA/B
input logic [2:0] Funct3E, Funct3M,
input logic MDUE, W64E,
output logic DivSM,
output logic FDivBusyE, IFDivStartE, FDivDoneE,
// output logic DivDone,
output logic [`NE+1:0] QeM,
output logic [`DIVb:0] QmM,
output logic [`XLEN-1:0] FPIntDivResultM
// output logic [`XLEN-1:0] RemM,
);
// Floating-point division and square root module, with optional integer division and remainder

11
pipelined/src/fpu/fdivsqrt/fdivsqrtfgen2.sv
View File

@ -37,15 +37,15 @@ module fdivsqrtfgen2 (
output logic [`DIVb+3:0] F
);
logic [`DIVb+3:0] FP, FN, FZ;
logic [`DIVb+3:0] SExt, SMExt, CExt;
logic [`DIVb+3:0] UExt, UMExt, CExt;
assign SExt = {3'b0, U};
assign SMExt = {3'b0, UM};
assign UExt = {3'b0, U};
assign UMExt = {3'b0, UM};
assign CExt = {2'b11, C}; // extend C from Q2.k to Q4.k
// Generate for both positive and negative bits
assign FP = ~(SExt << 1) & CExt;
assign FN = (SMExt << 1) | (CExt & ~(CExt << 2));
assign FP = ~(UExt << 1) & CExt;
assign FN = (UMExt << 1) | (CExt & ~(CExt << 2));
assign FZ = '0;
// Choose which adder input will be used
@ -54,5 +54,4 @@ module fdivsqrtfgen2 (
if (up) F = FP;
else if (uz) F = FZ;
else F = FN;
endmodule

9
pipelined/src/fpu/fdivsqrt/fdivsqrtpostproc.sv
View File

@ -121,13 +121,14 @@ module fdivsqrtpostproc(
end else begin
logic [`DIVb+3:0] PreIntQuotM;
if (WZeroM) begin
if (weq0M) begin
PreIntQuotM = weq0M ? {3'b000, FirstU} : {3'b000, FirstUM};
IntRemM = '0;
/* if (weq0M) begin
PreIntQuotM = {3'b000, FirstU};
IntRemM = '0;
end else begin
end else begin
PreIntQuotM = {3'b000, FirstUM};
IntRemM = '0;
end
end */
end else begin
PreIntQuotM = {3'b000, PreQmM};
IntRemM = NormRemM;