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switch linux-testbench infrastructure over to new linux testvectors at /opt/riscv

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This commit is contained in:
bbracker 2022-03-01 03:11:43 +00:00
parent a048dbb86b
commit a8e8cfb838
7 changed files with 28 additions and 24 deletions
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1
pipelined/config/buildroot/wally-config.vh
View File

@ -30,7 +30,6 @@
`define FPGA 1
`define QEMU 1
`define LINUX_FIX_READ {'h10000005}
`define LINUX_TEST_VECTORS "../../tests/linux-testgen/linux-testvectors/"
// RV32 or RV64: XLEN = 32 or 64
`define XLEN 64

8
pipelined/regression/regression-wally
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@ -48,19 +48,19 @@ def getBuildrootTC(short):
INSTR_LIMIT = 100000 # multiple of 100000
MAX_EXPECTED = 246000000
if short:
BRcmd="vsim > {} -c <<!\ndo wally-pipelined-batch.do buildroot buildroot "+str(INSTR_LIMIT)+" 1 0\n!"
BRcmd="vsim > {} -c <<!\ndo wally-pipelined-batch.do buildroot buildroot $RISCV "+str(INSTR_LIMIT)+" 1 0\n!"
BRgrepstr=str(INSTR_LIMIT)+" instructions"
else:
BRcmd="vsim > {} -c <<!\ndo wally-pipelined-batch.do buildroot buildroot 0 1 0\n!"
BRcmd="vsim > {} -c <<!\ndo wally-pipelined-batch.do buildroot buildroot $RISCV 0 1 0\n!"
BRgrepstr=str(MAX_EXPECTED)+" instructions"
return TestCase(name="buildroot",variant="rv64gc",cmd=BRcmd,grepstr=BRgrepstr)
tc = TestCase(
name="buildroot-checkpoint",
variant="rv64gc",
cmd="vsim > {} -c <<!\ndo wally-pipelined-batch.do buildroot buildroot-checkpoint 400100000 400000001 400000000\n!", # *** will this work with rv64gc rather than buildroot config?
cmd="vsim > {} -c <<!\ndo wally-pipelined-batch.do buildroot buildroot-checkpoint $RISCV 400100000 400000001 400000000\n!", # *** will this work with rv64gc rather than buildroot config?
grepstr="400100000 instructions")
configs.append(tc)
#configs.append(tc) #temporarily removed until I make this checkpoint
tests64gc = ["arch64i", "arch64priv", "arch64c", "arch64m", "arch64d", "imperas64i", "imperas64f", "imperas64d", "imperas64m", "imperas64a", "imperas64c", "wally64priv"] # , "imperas64mmu" "wally64i", #, "testsBP64"]
for test in tests64gc:

2
pipelined/regression/sim-buildroot
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@ -30,4 +30,4 @@ echo "INSTR_LIMIT = ${INSTR_LIMIT}"
echo "INSTR_WAVEON = ${INSTR_WAVEON}"
echo "CHECKPOINT = ${CHECKPOINT}"
vsim -do "do ./wally-pipelined.do buildroot buildroot $INSTR_LIMIT $INSTR_WAVEON $CHECKPOINT"
vsim -do "do ./wally-pipelined.do buildroot buildroot $RISCV $INSTR_LIMIT $INSTR_WAVEON $CHECKPOINT"

7
pipelined/regression/sim-buildroot-batch
View File

@ -30,10 +30,7 @@ echo "INSTR_LIMIT = ${INSTR_LIMIT}"
echo "INSTR_WAVEON = ${INSTR_WAVEON}"
echo "CHECKPOINT = ${CHECKPOINT}"
#vsim -c <<!
#do wally-buildroot-batch.do $INSTR_LIMIT $INSTR_WAVEON $CHECKPOINT
#!
# *** change config from buildroot to rv64gc
vsim -c <<!
do wally-pipelined-batch.do buildroot buildroot $INSTR_LIMIT $INSTR_WAVEON $CHECKPOINT
!
do wally-pipelined-batch.do buildroot buildroot $RISCV $INSTR_LIMIT $INSTR_WAVEON $CHECKPOINT
!

2
pipelined/regression/wally-pipelined-batch.do
View File

@ -35,7 +35,7 @@ vlib wkdir/work_${1}_${2}
if {$2 eq "buildroot" || $2 eq "buildroot-checkpoint"} {
vlog -lint -work wkdir/work_${1}_${2} +incdir+../config/$1 +incdir+../config/shared ../testbench/testbench-linux.sv ../testbench/common/*.sv ../src/*/*.sv ../src/*/*/*.sv -suppress 2583
# start and run simulation
vopt wkdir/work_${1}_${2}.testbench -work wkdir/work_${1}_${2} -G INSTR_LIMIT=$3 -G INSTR_WAVEON=$4 -G CHECKPOINT=$5 -o testbenchopt
vopt wkdir/work_${1}_${2}.testbench -work wkdir/work_${1}_${2} -G RISCV_DIR=$3 -G INSTR_LIMIT=$4 -G INSTR_WAVEON=$5 -G CHECKPOINT=$6 -o testbenchopt
vsim -lib wkdir/work_${1}_${2} testbenchopt -suppress 8852,12070,3084
run -all

2
pipelined/regression/wally-pipelined.do
View File

@ -34,7 +34,7 @@ vlib work
if {$2 eq "buildroot" || $2 eq "buildroot-checkpoint"} {
vlog -lint -work work_${1}_${2} +incdir+../config/$1 +incdir+../config/shared ../testbench/testbench-linux.sv ../testbench/common/*.sv ../src/*/*.sv ../src/*/*/*.sv -suppress 2583
# start and run simulation
vopt +acc work_${1}_${2}.testbench -work work_${1}_${2} -G INSTR_LIMIT=$3 -G INSTR_WAVEON=$4 -G CHECKPOINT=$5 -o testbenchopt
vopt +acc work_${1}_${2}.testbench -work work_${1}_${2} -G RISCV_DIR=$3 INSTR_LIMIT=$4 -G INSTR_WAVEON=$5 -G CHECKPOINT=$6 -o testbenchopt
vsim -lib work_${1}_${2} testbenchopt -suppress 8852,12070,3084
#-- Run the Simulation

30
pipelined/testbench/testbench-linux.sv
View File

@ -44,6 +44,7 @@ module testbench;
parameter INSTR_LIMIT = 0; // # of instructions at which to stop
parameter INSTR_WAVEON = 0; // # of instructions at which to turn on waves in graphical sim
parameter CHECKPOINT = 0;
parameter RISCV_DIR = "/opt/riscv";
///////////////////////////////////////////////////////////////////////////////
////////////////////////////////// HARDWARE ///////////////////////////////////
@ -111,6 +112,8 @@ module testbench;
integer errorCount = 0;
integer fault;
string ProgramAddrMapFile, ProgramLabelMapFile;
string testvectorDir;
string linuxImageDir;
// Checkpointing
string checkpointDir;
logic [1:0] initPriv;
@ -299,29 +302,34 @@ module testbench;
`INIT_CHECKPOINT_VAL(PRIV, [1:0]);
`MAKE_CHECKPOINT_INIT_SIGNAL(MSTATUS, [`XLEN-1:0],0,0);
integer ramFile;
integer memFile;
integer readResult;
initial begin
force dut.core.priv.priv.SwIntM = 0;
force dut.core.priv.priv.TimerIntM = 0;
force dut.core.priv.priv.ExtIntM = 0;
$readmemh({`LINUX_TEST_VECTORS,"bootmem.txt"}, dut.uncore.bootrom.bootrom.RAM, 'h1000 >> 3);
$sformat(testvectorDir,"%s/linux-testvectors/",RISCV_DIR);
$sformat(linuxImageDir,"%s/buildroot/output/images/",RISCV_DIR);
$readmemb(`TWO_BIT_PRELOAD, dut.core.ifu.bpred.bpred.Predictor.DirPredictor.PHT.mem);
$readmemb(`BTB_PRELOAD, dut.core.ifu.bpred.bpred.TargetPredictor.memory.mem);
ProgramAddrMapFile = {`LINUX_TEST_VECTORS,"vmlinux.objdump.addr"};
ProgramLabelMapFile = {`LINUX_TEST_VECTORS,"vmlinux.objdump.lab"};
ProgramAddrMapFile = {linuxImageDir,"vmlinux.objdump.addr"};
ProgramLabelMapFile = {linuxImageDir,"vmlinux.objdump.lab"};
// initialize bootrom
memFile = $fopen({testvectorDir,"bootmem.bin"}, "rb");
readResult = $fread(dut.uncore.bootrom.bootrom.RAM,memFile);
$fclose(memFile);
// initialize RAM
memFile = $fopen({testvectorDir,"ram.bin"}, "rb");
readResult = $fread(dut.uncore.ram.ram.RAM,memFile);
$fclose(memFile);
if (CHECKPOINT==0) begin // normal
$readmemh({`LINUX_TEST_VECTORS,"ram.txt"}, dut.uncore.ram.ram.RAM);
traceFileM = $fopen({`LINUX_TEST_VECTORS,"all.txt"}, "r");
traceFileE = $fopen({`LINUX_TEST_VECTORS,"all.txt"}, "r");
traceFileM = $fopen({testvectorDir,"all.txt"}, "r");
traceFileE = $fopen({testvectorDir,"all.txt"}, "r");
InstrCountW = '0;
end else begin // checkpoint
$sformat(checkpointDir,"checkpoint%0d/",CHECKPOINT);
checkpointDir = {`LINUX_TEST_VECTORS,checkpointDir};
checkpointDir = {testvectorDir,checkpointDir};
//$readmemh({checkpointDir,"ram.txt"}, dut.uncore.ram.ram.RAM);
ramFile = $fopen({checkpointDir,"ram.bin"}, "rb");
readResult = $fread(dut.uncore.ram.ram.RAM,ramFile);
$fclose(ramFile);
traceFileE = $fopen({checkpointDir,"all.txt"}, "r");
traceFileM = $fopen({checkpointDir,"all.txt"}, "r");
InstrCountW = CHECKPOINT;