forked from Github_Repos/cvw
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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commit
7dffcba182
@ -111,7 +111,7 @@ module ahblite (
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else if (IFUBusRead) NextBusState = INSTRREAD;
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else NextBusState = IDLE;
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INSTRREAD: if (~HREADY) NextBusState = INSTRREAD;
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else NextBusState = IDLE; // if (IFUBusRead still high)
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else NextBusState = IDLE; // if (IFUBusRead still high) *** need to wait?
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default: NextBusState = IDLE;
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endcase
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@ -21,10 +21,39 @@ hash := $(shell git rev-parse --short HEAD)
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export OUTPUTDIR := runs/$(DESIGN)_$(CONFIG)_$(TECH)nm_$(FREQ)_MHz_$(time)_$(hash)
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export SAIFPOWER ?= 0
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CONFIGDIR ?= ~/riscv-wally/pipelined/config
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#CONFIGS ?= $(shell find $(CONFIGDIR) -name "rv*")
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CONFIGS ?= ("rv32e", "rv32ic")
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print:
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echo "files in $(CONFIGDIR) are $(CONFIGS)."
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default:
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@echo "Basic synthesis procedure for OSU/HMC/UNLV:"
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@echo " adapt Makefile to your liking..."
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@echo
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@echo "Basic synthesis procedure for Wally:"
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@echo " Invoke with make synth"
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test: rv%
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echo "Running test on $<"
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rv%.log: rv%
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echo $<
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flavors:
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rm -rf $(CONFIGDIR)/rv32em
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cp -r $(CONFIGDIR)/rv32e $(CONFIGDIR)/rv32em
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sed -i 's/h00000010/h00001010/' $(CONFIGDIR)/rv32em/wally-config.vh
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# rv32e, 32ic, 32gc 64ic, 64gc
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# 64gc - FPU
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# PMP16
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# PMP0
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# No virtual memory
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# Muldiv
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allsynth:
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make flavors
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make synth DESIGN=wallypipelinedcore CONFIG=rv32e TECH=sky90 FREQ=500 MAXCORES=1
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make synth DESIGN=wallypipelinedcore CONFIG=rv32em TECH=sky90 FREQ=500 MAXCORES=1
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synth:
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@echo "DC Synthesis"
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