forked from Github_Repos/cvw
Moved conditional instantiation outside pmpchecker
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@ -107,15 +107,21 @@ module mmu #(parameter TLB_ENTRIES = 8, IMMU = 0) (
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.Cacheable, .Idempotent, .SelTIM,
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.PMAInstrAccessFaultF, .PMALoadAccessFaultM, .PMAStoreAmoAccessFaultM);
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pmpchecker pmpchecker(.PhysicalAddress, .PrivilegeModeW,
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.PMPCFG_ARRAY_REGW, .PMPADDR_ARRAY_REGW,
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.ExecuteAccessF, .WriteAccessM, .ReadAccessM,
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.PMPInstrAccessFaultF, .PMPLoadAccessFaultM, .PMPStoreAmoAccessFaultM);
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if (`PMP_ENTRIES > 0)
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pmpchecker pmpchecker(.PhysicalAddress, .PrivilegeModeW,
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.PMPCFG_ARRAY_REGW, .PMPADDR_ARRAY_REGW,
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.ExecuteAccessF, .WriteAccessM, .ReadAccessM,
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.PMPInstrAccessFaultF, .PMPLoadAccessFaultM, .PMPStoreAmoAccessFaultM);
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else begin
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assign PMPInstrAccessFaultF = 0;
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assign PMPStoreAmoAccessFaultM = 0;
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assign PMPLoadAccessFaultM = 0;
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end
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// Access faults
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// If TLB miss and translating we want to not have faults from the PMA and PMP checkers.
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assign InstrAccessFaultF = (PMAInstrAccessFaultF | PMPInstrAccessFaultF) & ~(Translate & ~TLBHit);
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assign LoadAccessFaultM = (PMALoadAccessFaultM | PMPLoadAccessFaultM) & ~(Translate & ~TLBHit);
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assign InstrAccessFaultF = (PMAInstrAccessFaultF | PMPInstrAccessFaultF) & ~(Translate & ~TLBHit);
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assign LoadAccessFaultM = (PMALoadAccessFaultM | PMPLoadAccessFaultM) & ~(Translate & ~TLBHit);
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assign StoreAmoAccessFaultM = (PMAStoreAmoAccessFaultM | PMPStoreAmoAccessFaultM) & ~(Translate & ~TLBHit);
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// Misaligned faults
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@ -49,34 +49,28 @@ module pmpchecker (
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output logic PMPStoreAmoAccessFaultM
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);
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if (`PMP_ENTRIES > 0) begin
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// Bit i is high when the address falls in PMP region i
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logic EnforcePMP;
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logic [`PMP_ENTRIES-1:0] Match; // physical address matches one of the pmp ranges
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logic [`PMP_ENTRIES-1:0] FirstMatch; // onehot encoding for the first pmpaddr to match the current address.
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logic [`PMP_ENTRIES-1:0] Active; // PMP register i is non-null
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logic [`PMP_ENTRIES-1:0] L, X, W, R; // PMP matches and has flag set
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logic [`PMP_ENTRIES-1:0] PAgePMPAdr; // for TOR PMP matching, PhysicalAddress > PMPAdr[i]
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// Bit i is high when the address falls in PMP region i
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logic EnforcePMP;
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logic [`PMP_ENTRIES-1:0] Match; // physical address matches one of the pmp ranges
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logic [`PMP_ENTRIES-1:0] FirstMatch; // onehot encoding for the first pmpaddr to match the current address.
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logic [`PMP_ENTRIES-1:0] Active; // PMP register i is non-null
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logic [`PMP_ENTRIES-1:0] L, X, W, R; // PMP matches and has flag set
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logic [`PMP_ENTRIES-1:0] PAgePMPAdr; // for TOR PMP matching, PhysicalAddress > PMPAdr[i]
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pmpadrdec pmpadrdecs[`PMP_ENTRIES-1:0](
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.PhysicalAddress,
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.PMPCfg(PMPCFG_ARRAY_REGW),
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.PMPAdr(PMPADDR_ARRAY_REGW),
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.PAgePMPAdrIn({PAgePMPAdr[`PMP_ENTRIES-2:0], 1'b1}),
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.PAgePMPAdrOut(PAgePMPAdr),
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.Match, .Active, .L, .X, .W, .R);
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pmpadrdec pmpadrdecs[`PMP_ENTRIES-1:0](
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.PhysicalAddress,
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.PMPCfg(PMPCFG_ARRAY_REGW),
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.PMPAdr(PMPADDR_ARRAY_REGW),
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.PAgePMPAdrIn({PAgePMPAdr[`PMP_ENTRIES-2:0], 1'b1}),
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.PAgePMPAdrOut(PAgePMPAdr),
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.Match, .Active, .L, .X, .W, .R);
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priorityonehot #(`PMP_ENTRIES) pmppriority(.a(Match), .y(FirstMatch)); // combine the match signal from all the adress decoders to find the first one that matches.
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priorityonehot #(`PMP_ENTRIES) pmppriority(.a(Match), .y(FirstMatch)); // combine the match signal from all the adress decoders to find the first one that matches.
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// Only enforce PMP checking for S and U modes when at least one PMP is active or in Machine mode when L bit is set in selected region
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assign EnforcePMP = (PrivilegeModeW == `M_MODE) ? |(L & FirstMatch) : |Active;
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// Only enforce PMP checking for S and U modes when at least one PMP is active or in Machine mode when L bit is set in selected region
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assign EnforcePMP = (PrivilegeModeW == `M_MODE) ? |(L & FirstMatch) : |Active;
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assign PMPInstrAccessFaultF = EnforcePMP & ExecuteAccessF & ~|(X & FirstMatch) ;
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assign PMPStoreAmoAccessFaultM = EnforcePMP & WriteAccessM & ~|(W & FirstMatch) ;
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assign PMPLoadAccessFaultM = EnforcePMP & ReadAccessM & ~|(R & FirstMatch) ;
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end else begin
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assign PMPInstrAccessFaultF = 0;
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assign PMPStoreAmoAccessFaultM = 0;
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assign PMPLoadAccessFaultM = 0;
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end
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assign PMPInstrAccessFaultF = EnforcePMP & ExecuteAccessF & ~|(X & FirstMatch) ;
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assign PMPStoreAmoAccessFaultM = EnforcePMP & WriteAccessM & ~|(W & FirstMatch) ;
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assign PMPLoadAccessFaultM = EnforcePMP & ReadAccessM & ~|(R & FirstMatch) ;
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endmodule
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