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Updated fpga constraints.

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This commit is contained in:
Ross Thompson 2022-12-21 14:50:01 -06:00
parent c7f3aae084
commit b7224cc5ba
2 changed files with 7 additions and 7 deletions
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2
fpga/constraints/debug2.xdc
View File

@ -316,7 +316,7 @@ connect_debug_port u_ila_0/probe60 [get_nets [list wallypipelinedsoc/core/hzu/IF
create_debug_port u_ila_0 probe
set_property port_width 1 [get_debug_ports u_ila_0/probe61]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe61]
connect_debug_port u_ila_0/probe61 [get_nets [list wallypipelinedsoc/core/hzu/FStallD ]]
connect_debug_port u_ila_0/probe61 [get_nets [list wallypipelinedsoc/core/hzu/FPUStallD ]]
create_debug_port u_ila_0 probe
set_property port_width 1 [get_debug_ports u_ila_0/probe62]

12
fpga/generator/Makefile
View File

@ -1,13 +1,13 @@
dst := IP
# vcu118
#export XILINX_PART := xcvu9p-flga2104-2L-e
#export XILINX_BOARD := xilinx.com:vcu118:part0:2.4
#export board := vcu118
export XILINX_PART := xcvu9p-flga2104-2L-e
export XILINX_BOARD := xilinx.com:vcu118:part0:2.4
export board := vcu118
# vcu108
export XILINX_PART := xcvu095-ffva2104-2-e
export XILINX_BOARD := xilinx.com:vcu108:part0:1.2
export board := vcu108
#export XILINX_PART := xcvu095-ffva2104-2-e
#export XILINX_BOARD := xilinx.com:vcu108:part0:1.2
#export board := vcu108
all: FPGA