Modified cache lru to not have the delayed write.

pipelined/src/cache/cache.sv

@@ -133,7 +133,7 @@ module cache #(parameter LINELEN,  NUMLINES,  NUMWAYS, LOGBWPL, WORDLEN, MUXINTE
     .Invalidate(InvalidateCache));
   if(NUMWAYS > 1) begin:vict
     cachereplacementpolicy #(NUMWAYS, SETLEN, OFFSETLEN, NUMLINES) cachereplacementpolicy(
-      .clk, .reset, .HitWay, .VictimWay, .RAdr, .LRUWriteEn);
+      .clk, .reset, .ce(SRAMEnable), .HitWay, .VictimWay, .RAdr, .LRUWriteEn);
   end else assign VictimWay = 1'b1; // one hot.
   assign CacheHit = | HitWay;
   assign VictimDirty = | VictimDirtyWay;

pipelined/src/cache/cachereplacementpolicy.sv

@@ -31,7 +31,7 @@
 
 module cachereplacementpolicy
   #(parameter NUMWAYS = 4, SETLEN = 9, OFFSETLEN = 5, NUMLINES = 128)(
-   input logic                clk, reset,
+   input logic                clk, reset, ce,
    input logic [NUMWAYS-1:0]  HitWay,
    output logic [NUMWAYS-1:0] VictimWay,
    input logic [SETLEN-1:0]   RAdr,
@@ -51,17 +51,15 @@ module cachereplacementpolicy
       assert (NUMWAYS == 2 || NUMWAYS == 4) else $error("Only 2 or 4 ways supported");
   end
   
-  // Pipeline Delay Registers
-  flopr #(SETLEN) RAdrDelayReg(clk, reset, RAdr, RAdrD);
-  flopr #(1) LRUWriteEnDelayReg(clk, reset, LRUWriteEn, LRUWriteEnD);
-  flopr #(NUMWAYS-1) NewReplacementDelayReg(clk, reset, NewReplacement, NewReplacementD);
-
   // Replacement Bits: Register file
   // Needs to be resettable for simulation, but could omit reset for synthesis ***
-  always_ff @(posedge clk) 
+  always_ff @(posedge clk) begin
     if (reset) for (int set = 0; set < NUMLINES; set++) ReplacementBits[set] <= '0;
-    else if (LRUWriteEnD) ReplacementBits[RAdrD] <= NewReplacementD;
-  assign LineReplacementBits = ReplacementBits[RAdrD];
+    if(ce) begin
+      LineReplacementBits <= #1 ReplacementBits[RAdr];
+      if (LRUWriteEn) ReplacementBits[RAdr] <= NewReplacement;
+    end
+  end  
 
   genvar 		      index;
   if(NUMWAYS == 2) begin : PseudoLRU