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Waiting on fix for wally64periph uart test.

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would like to remove vectored interrupt adder.
This commit is contained in:
Ross Thompson 2022-12-21 13:16:09 -06:00
parent 0b4186f1e8
commit c3b43b2fac
3 changed files with 8 additions and 4 deletions
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6
pipelined/src/privileged/csr.sv
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@ -143,8 +143,10 @@ module csr #(parameter
logic VectoredM;
logic [`XLEN-1:0] TVecPlusCauseM;
assign VectoredM = InterruptM & (TVecM[1:0] == 2'b01);
//assign TVecPlusCauseM = TVecAlignedM + {{(`XLEN-2-`LOG_XLEN){1'b0}}, CauseM, 2'b00};
assign TVecPlusCauseM = {TVecAlignedM[`XLEN-1:6], CauseM[3:0], 2'b00};
// *** Would like you use concat version, but breaks uart test wally64priv when
// mtvec is aligned to 64 bytes.
assign TVecPlusCauseM = TVecAlignedM + {{(`XLEN-2-`LOG_XLEN){1'b0}}, CauseM, 2'b00};
//assign TVecPlusCauseM = {TVecAlignedM[`XLEN-1:6], CauseM[3:0], 2'b00};
mux2 #(`XLEN) trapvecmux(TVecAlignedM, TVecPlusCauseM, VectoredM, TrapVectorM);
end else
assign TrapVectorM = TVecAlignedM;

3
tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-TEST-LIB-32.h
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@ -299,7 +299,8 @@ end_trap_triggers:
// --------------------------------------------------------------------------------------------
.align 6
//.align 6
.align 2
trap_handler_\MODE\():
j trap_unvectored_\MODE\() // for the unvectored implimentation: jump past this table of addresses into the actual handler
// *** ASSUMES that a cause value of 0 for an interrupt is unimplemented

3
tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-TEST-LIB-64.h
View File

@ -293,7 +293,8 @@ end_trap_triggers:
//
// --------------------------------------------------------------------------------------------
.align 6
//.align 6
.align 3
trap_handler_\MODE\():
j trap_unvectored_\MODE\() // for the unvectored implimentation: jump past this table of addresses into the actual handler
// *** ASSUMES that a cause value of 0 for an interrupt is unimplemented