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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main

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This commit is contained in:
David Harris 2022-05-17 15:09:52 +00:00
commit a2280dadfd
5 changed files with 150 additions and 34 deletions
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4
pipelined/config/rv64gc/wally-config.vh
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@ -131,8 +131,8 @@
`define PLIC_GPIO_ID 3
`define PLIC_UART_ID 10
`define TWO_BIT_PRELOAD "../config/rv64ic/twoBitPredictor.txt"
`define BTB_PRELOAD "../config/rv64ic/BTBPredictor.txt"
`define TWO_BIT_PRELOAD "../config/shared/twoBitPredictor.txt"
`define BTB_PRELOAD "../config/shared/BTBPredictor.txt"
`define BPRED_ENABLED 1
`define BPTYPE "BPGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE
`define TESTSBP 0

80
pipelined/src/ppa/ppa.sv
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@ -3,6 +3,14 @@
// & mmasserfrye@hmc.edu
// Measure PPA of various building blocks
module ppa_comparator_8 #(parameter WIDTH=8) (
input logic [WIDTH-1:0] a, b,
input logic sgnd,
output logic [1:0] flags);
ppa_comparator #(WIDTH) comp (.*);
endmodule
module ppa_comparator_16 #(parameter WIDTH=16) (
input logic [WIDTH-1:0] a, b,
input logic sgnd,
@ -27,6 +35,14 @@ module ppa_comparator_64 #(parameter WIDTH=64) (
ppa_comparator #(WIDTH) comp (.*);
endmodule
module ppa_comparator_128 #(parameter WIDTH=128) (
input logic [WIDTH-1:0] a, b,
input logic sgnd,
output logic [1:0] flags);
ppa_comparator #(WIDTH) comp (.*);
endmodule
module ppa_comparator #(parameter WIDTH=16) (
input logic [WIDTH-1:0] a, b,
input logic sgnd,
@ -45,6 +61,13 @@ module ppa_comparator #(parameter WIDTH=16) (
assign flags = {eq, lt};
endmodule
module ppa_add_8 #(parameter WIDTH=8) (
input logic [WIDTH-1:0] a, b,
output logic [WIDTH-1:0] y);
assign y = a + b;
endmodule
module ppa_add_16 #(parameter WIDTH=16) (
input logic [WIDTH-1:0] a, b,
output logic [WIDTH-1:0] y);
@ -66,6 +89,19 @@ module ppa_add_64 #(parameter WIDTH=64) (
assign y = a + b;
endmodule
module ppa_add_128 #(parameter WIDTH=128) (
input logic [WIDTH-1:0] a, b,
output logic [WIDTH-1:0] y);
assign y = a + b;
endmodule
module ppa_mult_8 #(parameter WIDTH=8) (
input logic [WIDTH-1:0] a, b,
output logic [WIDTH*2-1:0] y); //is this right width
assign y = a * b;
endmodule
module ppa_mult_16 #(parameter WIDTH=16) (
input logic [WIDTH-1:0] a, b,
output logic [WIDTH*2-1:0] y); //is this right width
@ -84,6 +120,12 @@ module ppa_mult_64 #(parameter WIDTH=64) (
assign y = a * b;
endmodule
module ppa_mult_128 #(parameter WIDTH=128) (
input logic [WIDTH-1:0] a, b,
output logic [WIDTH*2-1:0] y); //is this right width
assign y = a * b;
endmodule
module ppa_alu_16 #(parameter WIDTH=16) (
input logic [WIDTH-1:0] A, B,
input logic [2:0] ALUControl,
@ -180,6 +222,15 @@ module ppa_shiftleft #(parameter WIDTH=32) (
assign y = a << amt;
endmodule
module ppa_shifter_8 #(parameter WIDTH=8) (
input logic [WIDTH-1:0] A,
input logic [$clog2(WIDTH)-1:0] Amt,
input logic Right, Arith, W64,
output logic [WIDTH-1:0] Y);
ppa_shifter #(WIDTH) sh (.*);
endmodule
module ppa_shifter_16 #(parameter WIDTH=16) (
input logic [WIDTH-1:0] A,
input logic [$clog2(WIDTH)-1:0] Amt,
@ -207,6 +258,15 @@ module ppa_shifter_64 #(parameter WIDTH=64) (
ppa_shifter #(WIDTH) sh (.*);
endmodule
module ppa_shifter_128 #(parameter WIDTH=128) (
input logic [WIDTH-1:0] A,
input logic [$clog2(WIDTH)-1:0] Amt,
input logic Right, Arith, W64,
output logic [WIDTH-1:0] Y);
ppa_shifter #(WIDTH) sh (.*);
endmodule
module ppa_shifter #(parameter WIDTH=32) (
input logic [WIDTH-1:0] A,
input logic [$clog2(WIDTH)-1:0] Amt,
@ -221,14 +281,7 @@ module ppa_shifter #(parameter WIDTH=32) (
// For RV64, 32 and 64-bit shifts are needed, with sign extension.
// funnel shifter input (see CMOS VLSI Design 4e Section 11.8.1, note Table 11.11 shift types wrong)
if (WIDTH==32) begin:shifter // RV32
always_comb // funnel mux
if (Right)
if (Arith) z = {{31{A[31]}}, A};
else z = {31'b0, A};
else z = {A, 31'b0};
assign amttrunc = Amt; // shift amount
end else begin:shifter // RV64
if (WIDTH == 64) begin:shifter // RV64 fix what about 128
always_comb // funnel mux
if (W64) begin // 32-bit shifts
if (Right)
@ -241,8 +294,15 @@ module ppa_shifter #(parameter WIDTH=32) (
else z = {63'b0, A};
else z = {A, 63'b0};
end
assign amttrunc = W64 ? {1'b0, Amt[4:0]} : Amt; // 32 or 64-bit shift
end
end else begin:shifter // RV32,
always_comb // funnel mux
if (Right)
if (Arith) z = {{WIDTH-1{A[WIDTH-1]}}, A};
else z = {{WIDTH-1{1'b0}}, A};
else z = {A, {WIDTH-1{1'b0}}};
assign amttrunc = Amt; // shift amount
end
assign amttrunc = (W64 & WIDTH==64) ? {1'b0, Amt[4:0]} : Amt; // 32 or 64-bit shift fix
// opposite offset for right shfits
assign offset = Right ? amttrunc : ~amttrunc;

18
pipelined/testbench/testbench.sv
View File

@ -327,11 +327,21 @@ logic [3:0] dummy;
.done(DCacheFlushDone));
// initialize the branch predictor
if (`BPRED_ENABLED == 1)
if (`BPRED_ENABLED == 1)
initial begin
$readmemb(`TWO_BIT_PRELOAD, dut.core.ifu.bpred.bpred.Predictor.DirPredictor.PHT.mem);
$readmemb(`BTB_PRELOAD, dut.core.ifu.bpred.bpred.TargetPredictor.memory.mem);
end
integer adrindex;
// Initializing all zeroes into the branch predictor memory.
for(adrindex = 0; adrindex < 1024; adrindex++) begin
force dut.core.ifu.bpred.bpred.Predictor.DirPredictor.PHT.mem[adrindex] = 0;
force dut.core.ifu.bpred.bpred.TargetPredictor.memory.mem[adrindex] = 0;
end
#1;
for(adrindex = 0; adrindex < 1024; adrindex++) begin
release dut.core.ifu.bpred.bpred.Predictor.DirPredictor.PHT.mem[adrindex];
release dut.core.ifu.bpred.bpred.TargetPredictor.memory.mem[adrindex];
end
end
endmodule
module riscvassertions;

2
pipelined/testbench/tests.vh
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@ -962,7 +962,7 @@ string imperas32f[] = '{
"rv64i_m/I/andi-01", "6010",
"rv64i_m/I/auipc-01", "2010",
"rv64i_m/I/beq-01", "47010",
"rv64i_m/I/bge-01", "46010",
"rv64i_m/I/bge-01", "47010",
"rv64i_m/I/bgeu-01", "56010",
"rv64i_m/I/blt-01", "4d010",
"rv64i_m/I/bltu-01", "57010",

80
synthDC/ppa.py
View File

@ -1,28 +1,37 @@
#!/usr/bin/python3
# from msilib.schema import File
#from msilib.schema import File
import subprocess
from multiprocessing import Pool
import csv
import re
# import matplotlib.pyplot as plt
# import numpy as np
import matplotlib.pyplot as plt
import numpy as np
print("hi")
def run_command(module, width, freq):
command = "make synth DESIGN=ppa_{}_{} TECH=sky90 DRIVE=INV FREQ={} MAXOPT=1".format(module, width, freq)
def run_command(module, width, tech, freq):
command = "make synth DESIGN=ppa_{}_{} TECH={} DRIVE=INV FREQ={} MAXOPT=1".format(module, width, tech, freq)
subprocess.Popen(command, shell=True)
widths = ['16']
modules = ['shifter']
freqs = ['10']
def deleteRedundant(LoT):
'''not working'''
synthStr = "rm -rf runs/ppa_{}_{}_rv32e_{}_{}_*"
for synth in LoT:
print(synth)
bashCommand = synthStr.format(*synth)
outputCPL = subprocess.check_output(['bash','-c', bashCommand])
widths = ['8']
modules = ['add']
freqs = ['10']
tech = 'sky90'
LoT = []
for module in modules:
for width in widths:
for freq in freqs:
LoT += [[module, width, freq]]
LoT += [[module, width, tech, freq]]
deleteRedundant(LoT)
pool = Pool()
pool.starmap(run_command, LoT)
@ -45,13 +54,11 @@ allSynths = []
for i in range(len(linesCPL)):
line = linesCPL[i]
oneSynth = []
mwm = wm.findall(line)[0][4:-4].split('_')
oneSynth += [mwm[0]]
oneSynth += [mwm[1]]
oneSynth += [f.findall(line)[0][1:-4]]
oneSynth += cpl.findall(line)
oneSynth += da.findall(linesDA[i])
oneSynth = [mwm[0], int(mwm[1])]
oneSynth += [int(f.findall(line)[0][1:-4])]
oneSynth += [float(cpl.findall(line)[0])]
oneSynth += [float(da.findall(linesDA[i])[0])]
allSynths += [oneSynth]
file = open("ppaData.csv", "w")
@ -61,4 +68,43 @@ writer.writerow(['Module', 'Width', 'Target Freq', 'Delay', 'Area'])
for one in allSynths:
writer.writerow(one)
file.close()
file.close()
def plotPPA(module, freq, var):
'''
module: string module name
freq: int freq (GHz)
var: string 'delay' or 'area'
plots chosen variable vs width for all matching syntheses with regression
'''
global allSynths
ind = 3 if (var == 'delay') else 4
widths = []
ivar = []
for oneSynth in allSynths:
if (oneSynth[0] == module) & (oneSynth[2] == freq):
widths += [oneSynth[1]]
ivar += [oneSynth[ind]]
x = np.array(widths, dtype=np.int)
y = np.array(ivar, dtype=np.float)
A = np.vstack([x, np.ones(len(x))]).T
m, c = np.linalg.lstsq(A, y, rcond=None)[0]
z = np.polyfit(x, y, 2)
p = np.poly1d(z)
xp = np.linspace(0, 140, 200)
_ = plt.plot(x, y, 'o', label=module, markersize=10)
_ = plt.plot(x, m*x + c, 'r', label='Linear fit')
_ = plt.plot(xp, p(xp), label='Quadratic fit')
_ = plt.legend()
_ = plt.xlabel("Width (bits)")
_ = plt.ylabel(str.title(var))
plt.show()
plotPPA('add', 5000, 'delay')