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Moved IDIV in fdivsqrtfms into generate block

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David Harris 2022-12-27 22:04:50 -08:00
parent a832605658
commit 9964fc9ebe
1 changed files with 2 additions and 1 deletions
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pipelined/src/fpu/fdivsqrt/fdivsqrtfsm.sv
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@ -103,7 +103,8 @@ module fdivsqrtfsm(
always_comb begin
if (SqrtE) fbits = Nf + 2 + 2; // Nf + two fractional bits for round/guard + 2 for right shift by up to 2
else fbits = Nf + 2 + `LOGR; // Nf + two fractional bits for round/guard + integer bits - try this when placing results in msbs
cycles = MDUE ? (nE + 1) : (fbits + (`LOGR*`DIVCOPIES)-1)/(`LOGR*`DIVCOPIES);
if (`IDIV_ON_FPU) cycles = MDUE ? (nE + 1) : (fbits + (`LOGR*`DIVCOPIES)-1)/(`LOGR*`DIVCOPIES);
else cycles = (fbits + (`LOGR*`DIVCOPIES)-1)/(`LOGR*`DIVCOPIES);
end
/* verilator lint_on WIDTH */