Removed comment about nonexistent possible bug

2022-11-14 09:56:33 -08:00 · 2022-11-14 09:56:33 -08:00 · 895ee3d773
commit 895ee3d773
parent cae3e00751
1 changed files with 0 additions and 1 deletions
--- a/pipelined/src/mmu/hptw.sv
+++ b/pipelined/src/mmu/hptw.sv
@ -223,7 +223,6 @@ module hptw (
 	if (`XLEN == 32) begin
 		assign InitialWalkerState = L1_ADR;
 		assign MegapageMisaligned = |(CurrentPPN[9:0]); // must have zero PPN0
-			// *** Possible bug - should be L1_ADR?  If so, applies to 64 bits as well
 		assign Misaligned = ((WalkerState == L0_ADR) & MegapageMisaligned);
 	end else begin
 		logic  GigapageMisaligned, TerapageMisaligned;