forked from Github_Repos/cvw
Added if generate around bp logic only used with performance counters.
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@ -88,9 +88,8 @@ module bpred (
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logic BTBTargetWrongE;
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logic RASTargetWrongE;
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logic JumpOrTakenBranchE;
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logic [`XLEN-1:0] BTAD, BTAE, RASPCD, RASPCE;
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logic [`XLEN-1:0] BTAD;
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// Part 1 branch direction prediction
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// look into the 2 port Sram model. something is wrong.
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@ -243,26 +242,33 @@ module bpred (
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if(`INSTR_CLASS_PRED) mux2 #(`XLEN) pcmuxBPWrongInvalidateFlush(PCE, PCF, BPPredWrongM, NextValidPCE);
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else assign NextValidPCE = PCE;
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// performance counters
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// 1. class (class wrong / minstret) (PredictionInstrClassWrongM / csr) // Correct now
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// 2. target btb (btb target wrong / class[0,1,3]) (btb target wrong / (br + j + jal)
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// 3. target ras (ras target wrong / class[2])
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// 4. direction (br dir wrong / class[0])
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// Unforuantely we can't use PCD to infer the correctness of the BTB or RAS because the class prediction
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// could be wrong or the fall through address selected for branch predict not taken.
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// By pipeline the BTB's PC and RAS address through the pipeline we can measure the accuracy of
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// both without the above inaccuracies.
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assign BTBPredPCWrongE = (BTAE != IEUAdrE) & (InstrClassE[0] | InstrClassE[1] & ~InstrClassE[2]) & PCSrcE;
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assign RASPredPCWrongE = (RASPCE != IEUAdrE) & InstrClassE[2] & PCSrcE;
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if(`ZICOUNTERS_SUPPORTED) begin
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logic JumpOrTakenBranchE;
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logic [`XLEN-1:0] BTAE, RASPCD, RASPCE;
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// performance counters
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// 1. class (class wrong / minstret) (PredictionInstrClassWrongM / csr) // Correct now
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// 2. target btb (btb target wrong / class[0,1,3]) (btb target wrong / (br + j + jal)
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// 3. target ras (ras target wrong / class[2])
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// 4. direction (br dir wrong / class[0])
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assign JumpOrTakenBranchE = (InstrClassE[0] & PCSrcE) | InstrClassE[1];
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flopenrc #(1) JumpOrTakenBranchMReg(clk, reset, FlushM, ~StallM, JumpOrTakenBranchE, JumpOrTakenBranchM);
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// Unforuantely we can't use PCD to infer the correctness of the BTB or RAS because the class prediction
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// could be wrong or the fall through address selected for branch predict not taken.
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// By pipeline the BTB's PC and RAS address through the pipeline we can measure the accuracy of
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// both without the above inaccuracies.
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assign BTBPredPCWrongE = (BTAE != IEUAdrE) & (InstrClassE[0] | InstrClassE[1] & ~InstrClassE[2]) & PCSrcE;
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assign RASPredPCWrongE = (RASPCE != IEUAdrE) & InstrClassE[2] & PCSrcE;
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flopenrc #(`XLEN) BTBTargetEReg(clk, reset, FlushE, ~StallE, BTAD, BTAE);
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assign JumpOrTakenBranchE = (InstrClassE[0] & PCSrcE) | InstrClassE[1];
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flopenrc #(1) JumpOrTakenBranchMReg(clk, reset, FlushM, ~StallM, JumpOrTakenBranchE, JumpOrTakenBranchM);
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flopenrc #(`XLEN) RASTargetDReg(clk, reset, FlushD, ~StallD, RASPCF, RASPCD);
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flopenrc #(`XLEN) RASTargetEReg(clk, reset, FlushE, ~StallE, RASPCD, RASPCE);
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flopenrc #(`XLEN) BTBTargetEReg(clk, reset, FlushE, ~StallE, BTAD, BTAE);
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flopenrc #(`XLEN) RASTargetDReg(clk, reset, FlushD, ~StallD, RASPCF, RASPCD);
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flopenrc #(`XLEN) RASTargetEReg(clk, reset, FlushE, ~StallE, RASPCD, RASPCE);
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end else begin
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assign {BTBPredPCWrongE, RASPredPCWrongE, JumpOrTakenBranchM} = '0;
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end
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endmodule
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