Replaced FenceM with InvalidateICacheM for event counting of fence.i

src/ieu/controller.sv

@@ -66,7 +66,6 @@ module controller(
   output logic        RegWriteM,               // Instruction writes a register (needed for Hazard unit)
   output logic        InvalidateICacheM, FlushDCacheM, // Invalidate I$, flush D$
   output logic        InstrValidD, InstrValidE, InstrValidM, // Instruction is valid
-  output logic        FenceM,                  // Fence instruction
   output logic        FWriteIntM,              // FPU controller writes integer register file
   // Writeback stage control signals
   input  logic        StallW, FlushW,          // Stall, flush Writeback stage
@@ -116,6 +115,7 @@ module controller(
   logic        IFunctD, RFunctD, MFunctD;      // Detect I, R, and M-type RV32IM/Rv64IM instructions
   logic        LFunctD, SFunctD, BFunctD;      // Detect load, store, branch instructions
   logic        JFunctD;                        // detect jalr instruction
+  logic        FenceM;                         // Fence.I or sfence.VMA instruction in memory stage
 
   // Extract fields
   assign OpD = InstrD[6:0];
@@ -280,7 +280,6 @@ module controller(
 
   // Flush F, D, and E stages on a CSR write or Fence.I or SFence.VMA
   assign CSRWriteFenceM = CSRWriteM | FenceM;
-  //  assign CSRWriteFencePendingDEM = CSRWriteD | CSRWriteE | CSRWriteM | FenceD | FenceE | FenceM;
 
   // the synchronous DTIM cannot read immediately after write
   // a cache cannot read or write immediately after a write

src/ieu/ieu.sv

@@ -71,8 +71,7 @@ module ieu (
   output logic 		          FCvtIntStallD, LoadStallD,       // Stall causes from IEU to hazard unit
   output logic              MDUStallD, CSRRdStallD, StoreStallD,
   output logic 		          CSRReadM, CSRWriteM, PrivilegedM,// CSR read, CSR write, is privileged instruction
-  output logic 		          CSRWriteFenceM,                   // CSR write or fence instruction needs to flush subsequent instructions
-  output logic                FenceM
+  output logic 		          CSRWriteFenceM                   // CSR write or fence instruction needs to flush subsequent instructions
 );
 
   logic [2:0] ImmSrcD;                                       // Select type of immediate extension 
@@ -99,8 +98,8 @@ module ieu (
     .PCSrcE, .ALUControlE, .ALUSrcAE, .ALUSrcBE, .ALUResultSrcE, .MemReadE, .CSRReadE, 
     .Funct3E, .IntDivE, .MDUE, .W64E, .BranchD, .BranchE, .JumpD, .JumpE, .SCE, .BranchSignedE, .StallM, .FlushM, .MemRWM,
     .CSRReadM, .CSRWriteM, .PrivilegedM, .AtomicM, .Funct3M,
-    .RegWriteM, .InvalidateICacheM, .FlushDCacheM, .InstrValidM, .InstrValidE, .InstrValidD, .FWriteIntM,
-    .StallW, .FlushW, .RegWriteW, .IntDivW, .ResultSrcW, .CSRWriteFenceM, .FenceM, .StoreStallD);
+    .RegWriteM, .FlushDCacheM, .InstrValidM, .InstrValidE, .InstrValidD, .FWriteIntM,
+    .StallW, .FlushW, .RegWriteW, .IntDivW, .ResultSrcW, .CSRWriteFenceM, .InvalidateICacheM, .StoreStallD);
 
   datapath   dp(
     .clk, .reset, .ImmSrcD, .InstrD, .StallE, .FlushE, .ForwardAE, .ForwardBE,

src/privileged/csr.sv

@@ -72,7 +72,7 @@ module csr #(parameter
   input  logic             ICacheMiss,
   input  logic             ICacheAccess,
   input  logic             sfencevmaM,
-  input  logic             FenceM,
+  input  logic             InvalidateICacheM,
   input  logic             DivBusyE,                                  // integer divide busy
   input  logic             FDivBusyE,                                 // floating point divide busy
   // outputs from CSRs
@@ -268,7 +268,7 @@ module csr #(parameter
       .InstrValidNotFlushedM, .LoadStallD, .StoreStallD, .CSRWriteM, .CSRMWriteM,
       .BPDirPredWrongM, .BTAWrongM, .RASPredPCWrongM, .IClassWrongM, .BPWrongM,
       .InstrClassM, .DCacheMiss, .DCacheAccess, .ICacheMiss, .ICacheAccess, .sfencevmaM,
-      .InterruptM, .ExceptionM, .FenceM, .ICacheStallF, .DCacheStallM, .DivBusyE, .FDivBusyE,
+      .InterruptM, .ExceptionM, .InvalidateICacheM, .ICacheStallF, .DCacheStallM, .DivBusyE, .FDivBusyE,
       .CSRAdrM, .PrivilegeModeW, .CSRWriteValM,
       .MCOUNTINHIBIT_REGW, .MCOUNTEREN_REGW, .SCOUNTEREN_REGW,
       .MTIME_CLINT,  .CSRCReadValM, .IllegalCSRCAccessM);

src/privileged/csrc.sv

@@ -60,7 +60,7 @@ module csrc #(parameter
   input  logic              sfencevmaM,
   input  logic              InterruptM,
   input  logic              ExceptionM,
-  input  logic              FenceM,
+  input  logic              InvalidateICacheM,
   input  logic              DivBusyE,                                  // integer divide busy
   input  logic              FDivBusyE,                                 // floating point divide busy
   input  logic [11:0] 	    CSRAdrM,
@@ -111,7 +111,7 @@ module csrc #(parameter
     assign CounterEvent[17] = ICacheMiss;                                               // instruction cache miss. Miss asserted 1 cycle at start of cache miss
     assign CounterEvent[18] = ICacheStallF;                                             // i cache miss cycles
     assign CounterEvent[19] = CSRWriteM & InstrValidNotFlushedM;                        // CSR writes
-    assign CounterEvent[20] = FenceM & InstrValidNotFlushedM;                           // fence.i
+    assign CounterEvent[20] = InvalidateICacheM & InstrValidNotFlushedM;                           // fence.i
     assign CounterEvent[21] = sfencevmaM & InstrValidNotFlushedM;                       // sfence.vma
     assign CounterEvent[22] = InterruptM;                                               // interrupt, InstrValidNotFlushedM will be low
     assign CounterEvent[23] = ExceptionM;                                               // exceptions, InstrValidNotFlushedM will be low

src/privileged/privileged.sv

@@ -88,7 +88,7 @@ module privileged (
   // control outputs  
   output logic             RetM, TrapM,                               // return instruction, or trap
   output logic             sfencevmaM,                                // sfence.vma instruction
-  input  logic             FenceM,                                    // fence instruction
+  input  logic             InvalidateICacheM,                                    // fence instruction
   output logic             BigEndianM,                                // Use big endian in current privilege mode
   // Fault outputs
   output logic             BreakpointFaultM, EcallFaultM,             // breakpoint and Ecall traps should retire
@@ -131,7 +131,7 @@ module privileged (
     .MTimerInt, .MExtInt, .SExtInt, .MSwInt,
     .MTIME_CLINT, .InstrValidM, .FRegWriteM, .LoadStallD, .StoreStallD,
     .BPDirPredWrongM, .BTAWrongM, .RASPredPCWrongM, .BPWrongM,
-    .sfencevmaM, .ExceptionM, .FenceM, .ICacheStallF, .DCacheStallM, .DivBusyE, .FDivBusyE,
+    .sfencevmaM, .ExceptionM, .InvalidateICacheM, .ICacheStallF, .DCacheStallM, .DivBusyE, .FDivBusyE,
     .IClassWrongM, .InstrClassM, .DCacheMiss, .DCacheAccess, .ICacheMiss, .ICacheAccess,
     .NextPrivilegeModeM, .PrivilegeModeW, .CauseM, .SelHPTW,
     .STATUS_MPP, .STATUS_SPP, .STATUS_TSR, .STATUS_TVM,

src/wally/wallypipelinedcore.sv

@@ -161,7 +161,6 @@ module wallypipelinedcore (
   logic                          FCvtIntE;
   logic                          CommittedF;
   logic 						 BranchD, BranchE, JumpD, JumpE;
-  logic 						 FenceM;
   logic 						 DCacheStallM, ICacheStallF;
   
   // instruction fetch unit: PC, branch prediction, instruction cache
@@ -201,7 +200,7 @@ module wallypipelinedcore (
      .WriteDataM, // Write data to LSU
      .Funct3M, // size and signedness to LSU
      .SrcAM, // to privilege and fpu
-     .RdE, .RdM, .FIntResM, .InvalidateICacheM, .FlushDCacheM,
+     .RdE, .RdM, .FIntResM, .FlushDCacheM,
      .BranchD, .BranchE, .JumpD, .JumpE,
      // Writeback stage
      .CSRReadValW, .MDUResultW, .FIntDivResultW, .RdW, .ReadDataW(ReadDataW[`XLEN-1:0]),
@@ -209,7 +208,7 @@ module wallypipelinedcore (
      // hazards
      .StallD, .StallE, .StallM, .StallW, .FlushD, .FlushE, .FlushM, .FlushW,
      .FCvtIntStallD, .LoadStallD, .MDUStallD, .CSRRdStallD, .PCSrcE,
-     .CSRReadM, .CSRWriteM, .PrivilegedM, .CSRWriteFenceM, .FenceM, .StoreStallD); 
+     .CSRReadM, .CSRWriteM, .PrivilegedM, .CSRWriteFenceM, .InvalidateICacheM, .StoreStallD); 
 
   lsu lsu(
     .clk, .reset, .StallM, .FlushM, .StallW, .FlushW,
@@ -288,7 +287,7 @@ module wallypipelinedcore (
       .FlushD, .FlushE, .FlushM, .FlushW, .StallD, .StallE, .StallM, .StallW,
       .CSRReadM, .CSRWriteM, .SrcAM, .PCM, .PC2NextF,
       .InstrM, .CSRReadValW, .UnalignedPCNextF,
-      .RetM, .TrapM, .sfencevmaM, .FenceM, .DCacheStallM, .ICacheStallF,
+      .RetM, .TrapM, .sfencevmaM, .InvalidateICacheM, .DCacheStallM, .ICacheStallF,
       .InstrValidM, .CommittedM, .CommittedF,
       .FRegWriteM, .LoadStallD, .StoreStallD,
       .BPDirPredWrongM, .BTAWrongM, .BPWrongM,