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Modified rv32e configuration to use a true ahb bus interface in the lsu and ifu.

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This commit is contained in:
Ross Thompson 2022-08-29 17:04:53 -05:00
parent 4d7b905806
commit 4f40bd07c3
3 changed files with 30 additions and 4 deletions
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6
pipelined/src/ifu/ifu.sv
View File

@ -248,7 +248,9 @@ module ifu (
.s(SelUncachedAdr), .y(AllInstrRawF[31:0]));
end else begin : passthrough
assign IFUHADDR = PCPF;
flopen #(`XLEN) fb(.clk, .en(IFUBusRead), .d(HRDATA), .q(AllInstrRawF[31:0]));
logic CaptureEn;
flopen #(`XLEN) fb(.clk, .en(CaptureEn), .d(HRDATA), .q(AllInstrRawF[31:0]));
/* -----\/----- EXCLUDED -----\/-----
busfsm #(LOGBWPL) busfsm(
@ -258,7 +260,7 @@ module ifu (
.HTRANS(IFUHTRANS), .BusCommitted());
-----/\----- EXCLUDED -----/\----- */
AHBBusfsm busfsm(.HCLK(clk), .HRESETn(~reset), .RW(NonIROMMemRWM & ~{ITLBMissF, ITLBMissF}),
AHBBusfsm busfsm(.HCLK(clk), .HRESETn(~reset), .RW(NonIROMMemRWM & ~{ITLBMissF, ITLBMissF}), .CaptureEn,
.BusCommitted(), .CPUBusy, .HREADY(IFUHREADY), .BusStall, .HTRANS(IFUHTRANS), .HWRITE(IFUHWRITE));
assign IFUHBURST = 3'b0;

5
pipelined/src/lsu/lsu.sv
View File

@ -272,10 +272,11 @@ module lsu (
mux2 #(`XLEN) LSUHWDATAMux(.d0(ReadDataWordM[`XLEN-1:0]), .d1(LSUWriteDataM[`XLEN-1:0]),
.s(SelUncachedAdr), .y(LSUHWDATA));
end else begin : passthrough // just needs a register to hold the value from the bus
logic CaptureEn;
assign LSUHADDR = LSUPAdrM;
assign LSUHSIZE = LSUFunct3M;
flopen #(`XLEN) fb(.clk, .en(LSUBusRead), .d(HRDATA), .q(ReadDataWordM));
flopen #(`XLEN) fb(.clk, .en(CaptureEn), .d(HRDATA), .q(ReadDataWordM));
assign LSUHWDATA = LSUWriteDataM[`XLEN-1:0];
/* -----\/----- EXCLUDED -----\/-----
@ -287,7 +288,7 @@ module lsu (
-----/\----- EXCLUDED -----/\----- */
AHBBusfsm busfsm(.HCLK(clk), .HRESETn(~reset), .RW(LSURWM & ~{IgnoreRequest, IgnoreRequest}),
.BusCommitted(BusCommittedM), .CPUBusy, .BusStall, .HREADY(LSUHREADY), .HTRANS(LSUHTRANS),
.BusCommitted(BusCommittedM), .CPUBusy, .BusStall, .CaptureEn, .HREADY(LSUHREADY), .HTRANS(LSUHTRANS),
.HWRITE(LSUHWRITE));
assign ReadDataWordMuxM = LittleEndianReadDataWordM; // from byte swapping

23
pipelined/src/wally/wallypipelinedcore.sv
View File

@ -294,6 +294,7 @@ module wallypipelinedcore (
// *** Ross: please make EBU conditional when only supporting internal memories
if(`BUS) begin : ebu
/* -----\/----- EXCLUDED -----\/-----
ahblite ebu(// IFU connections
.clk, .reset,
.UnsignedLoadM(1'b0), .AtomicMaskedM(2'b00),
@ -320,6 +321,28 @@ module wallypipelinedcore (
.HREADY, .HRESP, .HCLK, .HRESETn,
.HADDR, .HWDATA, .HWSTRB, .HWRITE, .HSIZE, .HBURST,
.HPROT, .HTRANS, .HMASTLOCK);
-----/\----- EXCLUDED -----/\----- */
ahbmultimanager ebu(// IFU connections
.clk, .reset,
.IFUHADDR,
.IFUHBURST,
.IFUHTRANS,
.IFUHREADY,
// Signals from Data Cache
.LSUHADDR,
.LSUHWDATA,
.LSUHSIZE,
.LSUHBURST,
.LSUHTRANS,
.LSUHWRITE,
.LSUHREADY,
.HREADY, .HRESP, .HCLK, .HRESETn,
.HADDR, .HWDATA, .HWSTRB, .HWRITE, .HSIZE, .HBURST,
.HPROT, .HTRANS, .HMASTLOCK);
end