forked from Github_Repos/cvw
Reworked AHB fsm to support one cycle latency read and writes, renamed key signals to better reflect their use, and fixed HTRANS errors
This commit is contained in:
slmnemo
parent
284e0395a0
commit
054cf5f7b0
@ -45,10 +45,10 @@ module ahblite (
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input logic IFUBusRead,
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output logic [`XLEN-1:0] IFUBusHRDATA,
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output logic IFUBusAck,
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output logic IFUBusLock,
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output logic IFUBusInit,
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input logic [2:0] IFUBurstType,
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input logic [1:0] IFUTransType,
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input logic IFUBurstDone,
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input logic IFUTransComplete,
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// Signals from Data Cache
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input logic [`PA_BITS-1:0] LSUBusAdr,
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input logic LSUBusRead,
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@ -58,9 +58,9 @@ module ahblite (
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input logic [2:0] LSUBusSize,
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input logic [2:0] LSUBurstType,
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input logic [1:0] LSUTransType,
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input logic LSUBurstDone,
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input logic LSUTransComplete,
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output logic LSUBusAck,
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output logic LSUBusLock,
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output logic LSUBusInit,
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// AHB-Lite external signals
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(* mark_debug = "true" *) input logic [`AHBW-1:0] HRDATA,
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(* mark_debug = "true" *) input logic HREADY, HRESP,
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@ -79,11 +79,10 @@ module ahblite (
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(* mark_debug = "true" *) output logic HWRITED
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);
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typedef enum logic [2:0] {IDLE, MEMREAD, MEMREADNEXT, MEMWRITE, MEMWRITENEXT, INSTRREAD, INSTRREADNEXT} statetype;
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typedef enum logic [1:0] {IDLE, MEMREAD, MEMWRITE, INSTRREAD} statetype;
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statetype BusState, NextBusState;
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logic GrantData;
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logic SubsequentAccess;
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logic [31:0] AccessAddress;
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logic [2:0] ISize;
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@ -112,38 +111,27 @@ module ahblite (
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// interface that might be used in place of the ahblite.
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always_comb
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case (BusState)
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IDLE: if (LSUBusRead) NextBusState = MEMREAD; // Memory has priority over instructions
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else if (LSUBusWrite)NextBusState = MEMWRITE;
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else if (IFUBusRead) NextBusState = INSTRREAD;
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else NextBusState = IDLE;
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MEMREAD: if (HREADY) NextBusState = MEMREADNEXT;
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else NextBusState = MEMREAD;
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MEMREADNEXT: if (LSUBurstDone & ~(IFUBusRead & ~HREADY)) NextBusState = IDLE;
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else if (LSUBurstDone & IFUBusRead & HREADY) NextBusState = INSTRREAD;
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else if (HREADY) NextBusState = MEMREADNEXT;
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else NextBusState = MEMREAD;
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MEMWRITE: if (HREADY) NextBusState = MEMWRITENEXT;
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else NextBusState = MEMWRITE;
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MEMWRITENEXT: if (LSUBurstDone & ~(IFUBusRead & ~HREADY)) NextBusState = IDLE;
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else if (LSUBurstDone & IFUBusRead & HREADY) NextBusState = INSTRREAD;
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else if (HREADY) NextBusState = MEMWRITENEXT;
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else NextBusState = MEMWRITE;
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INSTRREAD: if (HREADY) NextBusState = INSTRREADNEXT;
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else NextBusState = INSTRREAD;
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INSTRREADNEXT: if (IFUBurstDone & ~LSUBusRead & ~LSUBusWrite) NextBusState = IDLE;
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else if (IFUBurstDone & LSUBusRead & HREADY) NextBusState = MEMREAD;
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else if (IFUBurstDone & LSUBusWrite & HREADY) NextBusState = MEMWRITE;
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else if (HREADY) NextBusState = INSTRREADNEXT;
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else NextBusState = INSTRREAD;
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default: NextBusState = IDLE;
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IDLE: if (LSUBusRead) NextBusState = MEMREAD; // Memory has priority over instructions
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else if (LSUBusWrite) NextBusState = MEMWRITE;
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else if (IFUBusRead) NextBusState = INSTRREAD;
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else NextBusState = IDLE;
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MEMREAD: if (LSUTransComplete & ~IFUBusRead) NextBusState = INSTRREAD;
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else if (LSUTransComplete) NextBusState = IDLE;
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else NextBusState = MEMREAD;
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MEMWRITE: if (LSUTransComplete & IFUBusRead) NextBusState = INSTRREAD;
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else if (LSUTransComplete) NextBusState = IDLE;
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else NextBusState = MEMWRITE;
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INSTRREAD: if (IFUTransComplete & LSUBusRead) NextBusState = MEMREAD;
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else if (IFUTransComplete & LSUBusWrite) NextBusState = MEMWRITE;
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else if (IFUTransComplete) NextBusState = IDLE;
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else NextBusState = INSTRREAD;
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default: NextBusState = IDLE;
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endcase
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// bus outputs
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assign #1 GrantData = (NextBusState == MEMREAD) | (NextBusState == MEMWRITE) |
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(NextBusState == MEMREADNEXT) | (NextBusState == MEMWRITENEXT);
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assign #1 GrantData = (NextBusState == MEMREAD) | (NextBusState == MEMWRITE);
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assign #1 AccessAddress = (GrantData) ? LSUBusAdr[31:0] : IFUBusAdr[31:0];
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assign #1 SubsequentAccess = (GrantData) ? |(AccessAddress[$clog2(`XLEN):0]) : |(AccessAddress[5:0]);
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assign #1 HADDR = AccessAddress;
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assign ISize = 3'b010; // 32 bit instructions for now; later improve for filling cache with full width; ignored on reads anyway
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assign HSIZE = (GrantData) ? {1'b0, LSUBusSize[1:0]} : ISize;
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@ -165,7 +153,7 @@ module ahblite (
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assign HPROT = 4'b0011; // not used; see Section 3.7
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assign HTRANS = (GrantData) ? LSUTransType : IFUTransType; // SEQ if not first read or write, NONSEQ if first read or write, IDLE otherwise
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assign HMASTLOCK = 0; // no locking supported
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assign HWRITE = (NextBusState == MEMWRITE) | (NextBusState == MEMWRITENEXT);
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assign HWRITE = (NextBusState == MEMWRITE);
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// delay write data by one cycle for
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flopen #(`XLEN) wdreg(HCLK, (IFUBusAck | LSUBusAck), LSUBusHWDATA, HWDATA); // delay HWDATA by 1 cycle per spec; *** assumes AHBW = XLEN
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// delay signals for subword writes
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@ -179,9 +167,9 @@ module ahblite (
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assign IFUBusHRDATA = HRDATA;
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assign LSUBusHRDATA = HRDATA;
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assign IFUBusLock = (NextBusState == INSTRREAD) | (NextBusState == INSTRREADNEXT);
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assign LSUBusLock = (NextBusState == MEMWRITENEXT) | (NextBusState == MEMREADNEXT) | (NextBusState == MEMREAD) | (NextBusState == MEMWRITE);
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assign IFUBusAck = (BusState == INSTRREADNEXT);
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assign LSUBusAck = (BusState == MEMREADNEXT) | (BusState == MEMWRITENEXT);
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assign IFUBusInit = (NextBusState == INSTRREAD);
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assign LSUBusInit = (NextBusState == MEMREAD) | (NextBusState == MEMWRITE);
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assign IFUBusAck = HREADY & (BusState == INSTRREAD);
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assign LSUBusAck = HREADY & ((BusState == MEMREAD) | (BusState == MEMWRITE));
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endmodule
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@ -38,13 +38,13 @@ module ifu (
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// Bus interface
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(* mark_debug = "true" *) input logic [`XLEN-1:0] IFUBusHRDATA,
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(* mark_debug = "true" *) input logic IFUBusAck,
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(* mark_debug = "true" *) input logic IFUBusLock,
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(* mark_debug = "true" *) input logic IFUBusInit,
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(* mark_debug = "true" *) output logic [`PA_BITS-1:0] IFUBusAdr,
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(* mark_debug = "true" *) output logic IFUBusRead,
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(* mark_debug = "true" *) output logic IFUStallF,
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(* mark_debug = "true" *) output logic [2:0] IFUBurstType,
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(* mark_debug = "true" *) output logic [1:0] IFUTransType,
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(* mark_debug = "true" *) output logic IFUBurstDone,
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(* mark_debug = "true" *) output logic IFUTransComplete,
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(* mark_debug = "true" *) output logic [`XLEN-1:0] PCF,
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// Execute
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output logic [`XLEN-1:0] PCLinkE,
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@ -205,8 +205,8 @@ module ifu (
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busdp #(WORDSPERLINE, LINELEN, LOGWPL, CACHE_ENABLED)
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busdp(.clk, .reset,
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.LSUBusHRDATA(IFUBusHRDATA), .LSUBusAck(IFUBusAck), .LSUBusLock(IFUBusLock), .LSUBusWrite(), .LSUBusWriteCrit(),
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.LSUBusRead(IFUBusRead), .LSUBusSize(), .LSUBurstType(IFUBurstType), .LSUTransType(IFUTransType), .LSUBurstDone(IFUBurstDone),
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.LSUBusHRDATA(IFUBusHRDATA), .LSUBusAck(IFUBusAck), .LSUBusInit(IFUBusInit), .LSUBusWrite(), .LSUBusWriteCrit(),
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.LSUBusRead(IFUBusRead), .LSUBusSize(), .LSUBurstType(IFUBurstType), .LSUTransType(IFUTransType), .LSUTransComplete(IFUTransComplete),
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.LSUFunct3M(3'b010), .LSUBusAdr(IFUBusAdr), .DCacheBusAdr(ICacheBusAdr),
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.WordCount(),
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.DCacheFetchLine(ICacheFetchLine),
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@ -40,13 +40,13 @@ module busdp #(parameter WORDSPERLINE, LINELEN, LOGWPL, CACHE_ENABLED)
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// bus interface
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input logic [`XLEN-1:0] LSUBusHRDATA,
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input logic LSUBusAck,
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input logic LSUBusLock,
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input logic LSUBusInit,
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output logic LSUBusWrite,
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output logic LSUBusRead,
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output logic [2:0] LSUBusSize,
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output logic [2:0] LSUBurstType,
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output logic [1:0] LSUTransType, // For AHBLite
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output logic LSUBurstDone,
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output logic LSUTransComplete,
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input logic [2:0] LSUFunct3M,
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output logic [`PA_BITS-1:0] LSUBusAdr, // ** change name to HADDR to make ahb lite.
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output logic [LOGWPL-1:0] WordCount,
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@ -89,6 +89,6 @@ module busdp #(parameter WORDSPERLINE, LINELEN, LOGWPL, CACHE_ENABLED)
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busfsm #(WordCountThreshold, LOGWPL, CACHE_ENABLED) busfsm(
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.clk, .reset, .IgnoreRequest, .LSURWM, .DCacheFetchLine, .DCacheWriteLine,
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.LSUBusAck, .LSUBusLock, .CPUBusy, .CacheableM, .BusStall, .LSUBusWrite, .LSUBusWriteCrit, .LSUBusRead,
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.LSUBurstType, .LSUTransType, .LSUBurstDone, .DCacheBusAck, .BusCommittedM, .SelUncachedAdr, .WordCount, .WordCountDelayed);
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.LSUBusAck, .LSUBusInit, .CPUBusy, .CacheableM, .BusStall, .LSUBusWrite, .LSUBusWriteCrit, .LSUBusRead,
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.LSUBurstType, .LSUTransType, .LSUTransComplete, .DCacheBusAck, .BusCommittedM, .SelUncachedAdr, .WordCount, .WordCountDelayed);
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endmodule
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@ -41,7 +41,7 @@ module busfsm #(parameter integer WordCountThreshold,
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input logic DCacheFetchLine,
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input logic DCacheWriteLine,
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input logic LSUBusAck,
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input logic LSUBusLock,
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input logic LSUBusInit,
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input logic CPUBusy,
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input logic CacheableM,
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@ -50,7 +50,7 @@ module busfsm #(parameter integer WordCountThreshold,
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output logic LSUBusWriteCrit,
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output logic LSUBusRead,
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output logic [2:0] LSUBurstType,
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output logic LSUBurstDone,
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output logic LSUTransComplete,
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output logic [1:0] LSUTransType,
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output logic DCacheBusAck,
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output logic BusCommittedM,
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@ -98,7 +98,7 @@ module busfsm #(parameter integer WordCountThreshold,
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assign NextWordCount = WordCount + 1'b1;
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assign WordCountFlag = (WordCountDelayed == WordCountThreshold[LOGWPL-1:0]);
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assign CntEn = PreCntEn & LSUBusAck | ((DCacheFetchLine | DCacheWriteLine) & LSUBusLock);
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assign CntEn = (PreCntEn & LSUBusAck | (LSUBusInit)) & ~WordCountFlag;
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assign UnCachedAccess = ~CACHE_ENABLED | ~CacheableM;
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@ -134,16 +134,17 @@ module busfsm #(parameter integer WordCountThreshold,
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always_comb begin
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case(WordCountThreshold)
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1: LocalBurstType = 3'b000;
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3: LocalBurstType = 3'b011; // INCR4
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7: LocalBurstType = 3'b101; // INCR8
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15: LocalBurstType = 3'b111; // INCR16
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default: LocalBurstType = 3'b000; // No Burst
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default: LocalBurstType = 3'b001; // No Burst
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endcase
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end
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assign LSUBurstType = (UnCachedAccess) ? 3'b0 : LocalBurstType ; // Don't want to use burst when doing an Uncached Access
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assign LSUBurstDone = (UnCachedAccess) ? LSUBusAck : WordCountFlag & LSUBusAck;
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assign LSUTransType = (|WordCount | |WordCountDelayed) ? 2'b11 : (LSUBusRead | LSUBusWrite) ? 2'b10 : 2'b00;
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assign LSUBurstType = (UnCachedAccess) ? 3'b0 : LocalBurstType ; // Don't want to use burst when doing an Uncached Access.
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assign LSUTransComplete = (UnCachedAccess) ? LSUBusAck : WordCountFlag & LSUBusAck;
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assign LSUTransType = (|WordCount) & ~UncachedAccess ? 2'b11 : (LSUBusRead | LSUBusWrite) & ~WordCountFlag ? 2'b10 : 2'b00;
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assign CntReset = BusCurrState == STATE_BUS_READY & ~(DCacheFetchLine | DCacheWriteLine);
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assign BusStall = (BusCurrState == STATE_BUS_READY & ~IgnoreRequest & ((UnCachedAccess & (|LSURWM)) | DCacheFetchLine | DCacheWriteLine)) |
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@ -66,13 +66,13 @@ module lsu (
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(* mark_debug = "true" *) output logic LSUBusRead,
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(* mark_debug = "true" *) output logic LSUBusWrite,
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(* mark_debug = "true" *) input logic LSUBusAck,
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(* mark_debug = "true" *) input logic LSUBusLock,
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(* mark_debug = "true" *) input logic LSUBusInit,
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(* mark_debug = "true" *) input logic [`XLEN-1:0] LSUBusHRDATA,
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(* mark_debug = "true" *) output logic [`XLEN-1:0] LSUBusHWDATA,
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(* mark_debug = "true" *) output logic [2:0] LSUBusSize,
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(* mark_debug = "true" *) output logic [2:0] LSUBurstType,
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(* mark_debug = "true" *) output logic [1:0] LSUTransType,
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(* mark_debug = "true" *) output logic LSUBurstDone,
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(* mark_debug = "true" *) output logic LSUTransComplete,
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// page table walker
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input logic [`XLEN-1:0] SATP_REGW, // from csr
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input logic STATUS_MXR, STATUS_SUM, STATUS_MPRV,
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@ -215,7 +215,7 @@ module lsu (
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busdp #(WORDSPERLINE, LINELEN, LOGWPL, CACHE_ENABLED) busdp(
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.clk, .reset,
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.LSUBusHRDATA, .LSUBusAck, .LSUBusLock, .LSUBusWrite, .LSUBusRead, .LSUBusSize, .LSUBurstType, .LSUTransType, .LSUBurstDone,
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.LSUBusHRDATA, .LSUBusAck, .LSUBusInit, .LSUBusWrite, .LSUBusRead, .LSUBusSize, .LSUBurstType, .LSUTransType, .LSUTransComplete,
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.WordCount, .LSUBusWriteCrit,
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.LSUFunct3M, .LSUBusAdr, .DCacheBusAdr, .DCacheFetchLine,
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.DCacheWriteLine, .DCacheBusAck, .DCacheBusWriteData, .LSUPAdrM,
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@ -134,16 +134,16 @@ module wallypipelinedcore (
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logic [`PA_BITS-1:0] IFUBusAdr;
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logic [`XLEN-1:0] IFUBusHRDATA;
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logic IFUBusRead;
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logic IFUBusAck, IFUBusLock;
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logic IFUBusAck, IFUBusInit;
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logic [2:0] IFUBurstType;
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logic [1:0] IFUTransType;
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logic IFUBurstDone;
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logic IFUTransComplete;
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// AHB LSU interface
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logic [`PA_BITS-1:0] LSUBusAdr;
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logic LSUBusRead;
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logic LSUBusWrite;
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logic LSUBusAck, LSUBusLock;
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logic LSUBusAck, LSUBusInit;
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logic [`XLEN-1:0] LSUBusHRDATA;
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logic [`XLEN-1:0] LSUBusHWDATA;
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@ -157,7 +157,7 @@ module wallypipelinedcore (
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logic [2:0] LSUBusSize;
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logic [2:0] LSUBurstType;
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logic [1:0] LSUTransType;
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logic LSUBurstDone;
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logic LSUTransComplete;
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logic DCacheMiss;
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logic DCacheAccess;
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@ -172,8 +172,8 @@ module wallypipelinedcore (
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.StallF, .StallD, .StallE, .StallM,
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.FlushF, .FlushD, .FlushE, .FlushM,
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// Fetch
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.IFUBusHRDATA, .IFUBusAck, .IFUBusLock, .PCF, .IFUBusAdr,
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.IFUBusRead, .IFUStallF, .IFUBurstType, .IFUTransType, .IFUBurstDone,
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.IFUBusHRDATA, .IFUBusAck, .IFUBusInit, .PCF, .IFUBusAdr,
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.IFUBusRead, .IFUStallF, .IFUBurstType, .IFUTransType, .IFUTransComplete,
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.ICacheAccess, .ICacheMiss,
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// Execute
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@ -253,8 +253,8 @@ module wallypipelinedcore (
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.IEUAdrE, .IEUAdrM, .WriteDataE,
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.ReadDataM, .FlushDCacheM,
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// connected to ahb (all stay the same)
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.LSUBusAdr, .LSUBusRead, .LSUBusWrite, .LSUBusAck, .LSUBusLock,
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.LSUBusHRDATA, .LSUBusHWDATA, .LSUBusSize, .LSUBurstType, .LSUTransType, .LSUBurstDone,
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.LSUBusAdr, .LSUBusRead, .LSUBusWrite, .LSUBusAck, .LSUBusInit,
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.LSUBusHRDATA, .LSUBusHWDATA, .LSUBusSize, .LSUBurstType, .LSUTransType, .LSUTransComplete,
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// connect to csr or privilege and stay the same.
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.PrivilegeModeW, .BigEndianM, // connects to csr
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@ -289,18 +289,18 @@ module wallypipelinedcore (
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.IFUBusHRDATA,
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.IFUBurstType,
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.IFUTransType,
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.IFUBurstDone,
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.IFUTransComplete,
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.IFUBusAck,
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.IFUBusLock,
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.IFUBusInit,
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// Signals from Data Cache
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.LSUBusAdr, .LSUBusRead, .LSUBusWrite, .LSUBusHWDATA,
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.LSUBusHRDATA,
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.LSUBusSize,
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.LSUBurstType,
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.LSUTransType,
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.LSUBurstDone,
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.LSUTransComplete,
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.LSUBusAck,
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.LSUBusLock,
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.LSUBusInit,
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.HRDATA, .HREADY, .HRESP, .HCLK, .HRESETn,
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.HADDR, .HWDATA, .HWRITE, .HSIZE, .HBURST,
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