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Fixed bug with combined dtim+bus.

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This commit is contained in:
Ross Thompson 2022-10-05 15:16:01 -05:00
parent b52ab91028
commit 2e578eb8d8
1 changed files with 1 additions and 1 deletions
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pipelined/src/lsu/lsu.sv
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@ -260,7 +260,7 @@ module lsu (
mux2 #(`LLEN) UnCachedDataMux(.d0(DCacheReadDataWordM), .d1({{`LLEN-`XLEN{1'b0}}, FetchBuffer[`XLEN-1:0] }),
.s(SelUncachedAdr), .y(ReadDataWordMuxM));
mux2 #(`LLEN) ReadDataMux2(.d0(ReadDataWordMuxM), .d1({{`LLEN-`XLEN{1'b0}}, DTIMReadDataWordM[`XLEN-1:0]}),
.s(SelUncachedAdr), .y(ReadDataWordMux2M));
.s(SelDTIM), .y(ReadDataWordMux2M));
mux2 #(`XLEN) LSUHWDATAMux(.d0(DCacheReadDataWordM[`XLEN-1:0]), .d1(LSUWriteDataM[`XLEN-1:0]),
.s(SelUncachedAdr), .y(PreHWDATA));